Functional error only
Debug error only
IVA2_IRQ[39]
M_IRQ_10
M_IRQ_9
interconnect-005
SGX
SGX MError
SGX SError
Public Version
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L3 Interconnect
NOTE:
The user must ensure that the corresponding IRQ lines are set correctly in the interrupt
controllers of the MPU and IVA2.2 subsystems.
shows the routing of errors to the application and debug error composite flags. Because both
debug capable processors, the MPU and IVA2.2 subsystems have access to the full error report
mechanism; they can be debugged independently of one another.
Figure 9-9. L3 Error Routing
lists the bit and source for the STATUS bit field
[63:0] for an
application error, and
lists the bit and source for the STATUS bit field
[63:0] for an application error for a debug error.
Protection errors are reported in-band to the IA when possible. This may not be possible for posted writes,
however. These errors are also reported asynchronously to the module.
Additionally, all protection errors (even posted writes) are seen by the in-band-to-out-of-band conversion
logic in the IAs. Therefore, all protection errors feed into the L3 application error and L3 debug error
composite flags, and hence back to the MPU and IVA2.2 subsystems.
The SMS, L4-Core, L-4 Per, and L4-Emu interconnects have internal firewalls that use the same reporting
scheme. These errors are not routed directly to the L3 interconnect but are reported in-band to the
initiator, which routes them to the composite flags. The SMS, L4-Core, L4-Per, and L4-Emu interconnects
always provide an error on the in-band SResp qualifier for protection violations.
Table 9-29. L3_SI_FLAG_STATUS_0 for Application Error
Flag Bit Number
Source
Flag Bit Number
Source
Agent
Error
Agent
Error
0
MPU IA
Burst time-out
32
Reserved
1
MPU IA
Response time-out
33
SAD2D IA
Burst time-out
2
MPU IA
Functional Inband
34
SAD2D IA
Response time-out
error
3
35
SAD2D IA
SError
4
Reserved
36
Reserved
5
37
Reserved
2019
SWPU177N – December 2009 – Revised November 2010
Interconnect
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