Texas Instruments OMAP36 Series, Technical Reference Manual

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L3 Interconnect
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Table 9-46. L3_IA_ERROR_LOG
Address Offset 0x058
Physical Address See Table 9-34 to Table 9-37
Description Error log register of IA block
Type RW
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
Reserved REQ_INFO
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CODE Reserved INITID Reserved CMD
MULTI
Reserved
SECONDARY
Bits Field Name Description Type Reset
63:48 Reserved Reserved R 0x0000
47:32 REQ_INFO MReqInfo bits of command that caused the error R 0x0000
31 MULTI Multiple Errors RW 0
Write 0x0: Ignored
Read 0x0: Multiple error not seen
Write 0x1: Clear MULTI flag
Read 0x1: Multiple error seen
30 SECONDARY Indicates whether error was primary or secondary RW 0
Write 0x0: Ignored
Read 0x0: Primary Error
Write 0x1: Reset SECONDARY field
Read 0x1: Secondary Error
29:28 Reserved Reserved R 0x0
27:24 CODE Error code RW 0x0
23:16 Reserved Reserved R 0x00
15:8 INITID Initiator ID from which the command was launched. See R 0x00
Table 9-19 .
7:3 Reserved Reserved R 0x00
2:0 CMD Command that caused the error R 0x0
Table 9-47. Register Call Summary for Register L3_IA_ERROR_LOG
L3 Interconnect
• Error Detection and Logging : [0]
• Error Steering : [1] [2] [3] [4]
• Time-Out Handling : [5] [6] [7] [8] [9] [10] [11]
• Acknowledging Errors : [12]
• L3 Initiator Agent (L3 IA) : [13] [14] [15] [16]
2034 Interconnect SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated