Texas Instruments OMAP36 Series, Technical Reference Manual

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Camera ISP Register Manual
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Table 6-286. HIST_CNT
Address Offset 0x0000 0008
Physical Address 0x480B CA08 Instance ISP_HIST
Description HISTOGRAM CONTROL REGISTER
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED BINS SHIFT
CLR CFA
DATSIZ
SOURCE
Bits Field Name Description Type Reset
31:9 RESERVED Write 0s for future compatibility. RW 0x000000
Reads returns 0.
8 DATSIZ Input data width RW 0x0
0x0: The pixels are coded on more than 8 bits.
0x1: The pixels are coded on 8 bits.
7 CLR Clear histogram data after read. RW 0x0
0x0: Don't clear the data after read.
0x1: Clear the data after read.
6 CFA CFA pattern. RW 0x0
0x0: Bayer pattern.
0x1: Reserved.
5:4 BINS Number of bins. RW 0x0
0x0: 32 bins, REGIONS 0, 1, 2 and 3 are active.
0x1: 64 bins, REGIONS 0, 1, 2 and 3 are active.
0x2: 128 bins, REGIONS 0 and 1 are active.
0x3: 256 bins, REGION 0 is active.
3 SOURCE Input source. RW 0x0
0x0: The input data comes from the CCDC module.
0x1: The input data comes from memory.
2:0 SHIFT Shift value. RW 0x0
The pixel data is right shifted before the binning
operation. The shift value can vary from 0 to 7.
Table 6-287. Register Call Summary for Register HIST_CNT
Camera ISP Functional Description
• Camera ISP Histogram Input Interface : [0] [1] [2]
• Camera ISP Histogram Binning : [3]
Camera ISP Basic Programming Model
• Camera ISP Histogram Reset of Histogram Output Memory : [7]
• Camera ISP Histogram Register Setup : [8] [9] [10] [11] [12] [13] [14] [15] [16]
Camera ISP Register Manual
• Camera ISP HIST Register Summary : [17]
1406 Camera Image Signal Processor SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated