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Camera ISP Basic Programming Model
6.5.10.1.3 Camera ISP Histogram Register Setup
Before enabling the histogram module, the hardware must be correctly configured through register writes.
identifies the register parameters that must be programmed before enabling the histogram.
Table 6-75. Camera ISP Histogram Required Configuration Parameters
Function
Configuration Required
Histogram Control Bits
[3] SOURCE
[6] CFA
[5:4] BINS
[2:0] SHIFT
[7] CLR
White Balance Gain
Region n Size and position (n = 0)
can be read as:
If (Condition is TRUE) then
Configuration required parameters should be programmed
Table 6-76. Camera ISP Histogram Conditional Configuration Parameters
Function
Condition
Configuration Required
Input from memory
[3] SOURCE = 0x1
[8] DATSIZ
Less than 256 bins
[5:4] BINS 3
(n = 1)
(n = 1)
Less than 128 bins
[5:4] BINS 2
(n = 2)
(n = 2)
(n = 3)
(n = 3)
6.5.10.2 Camera ISP Histogram Enable/Disable Hardware
Setting the
[0] ENABLE bit enables the histogram module. This must be done after all required
registers are programmed and the output memory has been cleared.
When the input source is the memory, the histogram module always operates in one-shot mode. In other
words, after enabling the histogram, the ENABLE bit is automatically turned off (set to 0) and only a single
frame is processed from memory. In this mode, fetching and processing of the frame begin immediately
on setting the ENABLE bit.
When the input source is the CCDC, the histogram always operates in continuous mode. Processing of
the frame depends on the timing of the CCDC. To ensure that data from the CCDC is not missed, the
histogram must be enabled before CCDC so it waits for CCDC data..
When the histogram is in continuous mode, it can be disabled by clearing the ENABLE bit during the
processing of the last frame. The disable is latched in at the end of the frame in which it is written.
6.5.10.3 Camera ISP Histogram Event and Status Checking
The histogram generates an interrupt at the end of each frame.
The status of this interrupt can be checked by reading the
register (or
). When the read of the register
occurs (or
), the
register is not automatically reset. To reset the interrupt, a 1 must be written to the HIST_DONE_IRQ bit.
1293
SWPU177N – December 2009 – Revised November 2010
Camera Image Signal Processor
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