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Camera ISP Register Manual
Bits
Field Name
Description
Type
Reset
31:10
RESERVED
Write 0s for future compatibility.
RW
0x000000
Reads returns 0.
9:0
ADDR
Histogram memory address.
RW
0x000
The histogram memory has 1024 entries. Each entry is
coded on 20 bits.
Table 6-295. Register Call Summary for Register HIST_ADDR
Camera ISP Functional Description
Camera ISP Register Manual
•
Camera ISP HIST Register Summary
:
Table 6-296. HIST_DATA
Address Offset
0x0000 0034
Physical Address
0x480B CA34
Instance
ISP_HIST
Description
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
RDATA
Bits
Field Name
Description
Type
Reset
31:20
RESERVED
Write 0s for future compatibility.
RW
0x000
Reads returns 0.
19:0
RDATA
Histogram data.
RW
0x-----
The histogram memory has 1024 entries. Each entry is
coded on 20 bits.
Table 6-297. Register Call Summary for Register HIST_DATA
Camera ISP Functional Description
Camera ISP Basic Programming Model
•
Camera ISP Histogram Register Accessibility During Frame Processing
Camera ISP Register Manual
•
Camera ISP HIST Register Summary
:
Table 6-298. HIST_RADD
Address Offset
0x0000 0038
Physical Address
0x480B CA38
Instance
ISP_HIST
Description
ADDRESS REGISTER This register is used only if the HIST module input data comes from memory
instead of the CCDC module.
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RADD
Bits
Field Name
Description
Type
Reset
31:0
RADD
32-bit address.
RW
0x00000000
The 5 LSBs are ignored: the starting address should be
aligned on a 32-byte boundary.
1409
SWPU177N – December 2009 – Revised November 2010
Camera Image Signal Processor
Copyright © 2009–2010, Texas Instruments Incorporated