Public Version
Camera ISP Register Manual
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Bits
Field Name
Description
Type
Reset
31:16
RESERVED
Write 0s for future compatibility. Read returns 0.
RW
0x0000
15:0
OFFSET
Defines the length, in bytes, of one row of the gain table.
RW
0x0000
Gain table is 32-bit aligned, so this value must be a
multiple of 4.
Note that the row in memory must be longer or equal to
what LSC uses.
Table 6-280. Register Call Summary for Register CCDC_LSC_TABLE_OFFSET
Camera ISP Functional Description
•
Camera ISP CCDC Functional Operations
Camera ISP Basic Programming Model
•
Camera ISP CCDC Register Setup
•
Camera ISP CCDC Register Accessibility During Frame Processing
•
Camera ISP CCDC Image-Signal Processing
Camera ISP Register Manual
•
Camera ISP CCDC Register Summary
6.6.5 Camera ISP HIST Registers
6.6.5.1
Camera ISP HIST Register Summary
Table 6-281. ISP_HIST Register Summary
Register Name
Type
Register Width (Bits)
Address Offset
Physical Address
R
32
0x0000 0000
0x480B CA00
RW
32
0x0000 0004
0x480B CA04
RW
32
0x0000 0008
0x480B CA08
RW
32
0x0000 000C
0x480B CA0C
(1)
RW
32
0x0000 0010 + (n*0x8)
0x480B CA10 + (n*0x8)
(1)
RW
32
0x0000 0014 + (n*0x8)
0x480B CA14 + (n*0x8)
RW
32
0x0000 0030
0x480B CA30
RW
32
0x0000 0034
0x480B CA34
RW
32
0x0000 0038
0x480B CA38
RW
32
0x0000 003C
0x480B CA3C
RW
32
0x0000 0040
0x480B CA40
(1)
n = 0 to 3
6.6.5.2
Camera ISP HIST Register Description
Table 6-282. HIST_PID
Address Offset
0x0000 0000
Physical Address
0x480B CA00
Instance
ISP_HIST
Description
PERIPHERAL ID REGISTER
Type
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
TID
CID
PREV
1404
Camera Image Signal Processor
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated