Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 1264 / 3738

camisp-083
PRESTROBE
STROBE
cam_strobe = PRESTROBE or STROBE ON OFF OFF OFF OFF
t1 t2
t3 t4
t5
cam_global_reset event
ON ON ON
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Camera ISP Basic Programming Model
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Figure 6-110. cam_strobe Signal-Generation for Red-Eye Removal
• t1: Set by the TCTRL_PSTRB_DELAY register
• t2: set by the TCTRL_PSTRB_LENGTH register
• t5: set by the TCTRL_PSTRB_REPLAY [24:0] DELAY bit field. The number of times the pulse is
repeated is controlled by the TCTRL_PSTRB_REPLAY [31:25] COUNTER register.
In the former example, TCTRL_PSTRB_REPLAY [31:25] COUNTER = 2.
– The possible delay values are 0 to 2
25
-1 cycle. The cycles are at the CNTCLK clock frequency.
The maximum signal duration is (2
25
-1) x 2.366 s = 79 s ( TCTRL_CTRL [18:11] DIVC = 511).
– The possible count values are 0 to 127 additional pulses.
• t3: Set by the TCTRL_STRB_DELAY register
• t4: Set by the TCTRL_STRB_LENGTH register
6.5.6 Programming the CCDC
This section discusses issues related to the software control of the CCDC. It lists which registers are
required to be programmed in different modes, and describes how to enable and disable the CCDC, how
to check the status of the CCDC, the different register access types, and programming constraints.
6.5.6.1 Camera ISP CCDC Hardware Setup/Initialization
This section discusses the configuration of the CCDC required before image processing can begin.
6.5.6.1.1 Camera ISP CCDC Reset Behavior
On hardware reset of the camera ISP, all registers in the CCDC are reset to their reset values.
6.5.6.1.2 Camera ISP CCDC Register Setup
Before enabling the CCDC, the hardware must be correctly configured through register writes. Table 6-61
identifies the register parameters that must be programmed before enabling the CCDC.
1264 Camera Image Signal Processor SWPU177N – December 2009 – Revised November 2010
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