Public Version
Camera ISP Basic Programming Model
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Each event that generates an interrupt can be individually mapped to ARM or DSP using the
register (or
). When a particular event is not enabled (for example
[x] = 0), the corresponding status (
[x] = 1) bit is flagged if the
corresponding event occurs. This has no effect on the interrupt line, but can be used by software to poll
the status.
The
[1] BUSY status bit is set when the start of frame occurs (if the
[0] ENABLE bit
is 1 at that time). It is automatically reset to 0 at the end of a frame. The
[1] BUSY status bit
may be polled to determine the end-of-frame status.
6.5.10.4 Camera ISP Histogram Register Accessibility During Frame Processing
There are two types of register access in the histogram module.
•
Shadow registers: These registers/fields can be read and written (if the field is writable) at any time.
However, the written values take effect only at the start of a frame. Reads return the most recent write,
even though the settings are not used until the next start of frame.
The shadowed registers are:
–
–
–
•
Busy-lock registers
–
All registers EXCEPT the shadowed registers belong to this category.
–
Busy-lock registers cannot be written when the module is busy. Writes are allowed, but no change
occurs in the registers (blocked writes from hardware perspective; allowed write from software
perspective).
–
After the
[1] BUSY bit is reset to 0, the busy-lock registers can be written.
–
The
register cannot be read when the histogram is busy, because since this register is
mapped to memories internally. Such reads return indeterminate data. Byte enables are not
implemented for reading the histogram memory.
The ideal procedure for changing the histogram registers is:
IF (
[1] BUSY == 0) OR IF (EOF interrupt occurs)
DISABLE HISTOGRAM
CHANGE REGISTERS
ENABLE HISTOGRAM
6.5.10.5 Camera ISP Histogram Interframe Operations
Between frames read from memory, it may be necessary to modify the input memory pointers before
processing the next frame. Since the
and memory pointer registers are shadowed, these
modifications can take place any time before the end of the frame, and the data is latched in for the next
frame. The MPU Subsystem can perform these changes on receiving an interrupt.
If continuous frames are processed without clearing the histogram output memory, the bin counters
contain the counts of however many images are processed since they were last cleared. To read the bin
counters for each frame, the bin counters must be read after each frame is completed, but before the next
frame begins (since the counters cannot be read while the
[1] BUSY bit is 1).
If the input source is memory (one-shot mode), the
[0] ENABLE bit must be set once for the
frame, and after the frame is completed, the bin counters can be read/cleared before enabling the next
frame.
When the input source is the video-port interface of the CCDC (continuous mode), the
[0]
ENABLE bit must be set to enable processing of the frame, and cleared after the frame processing begins
(the disable is latched in at the end of the frame). This procedure allows only one frame to be processed.
After the frame is completed, the bin counters can be read/cleared before enabling the histogram for the
next frame.
1294
Camera Image Signal Processor
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated