Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 466 / 3738

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PRCM Register Manual
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Bits Field Name Description Type Reset
31:1 RESERVED Write 0s for future compatibility. Read returns 0. R 0x00000000
0 CLKACTIVITY_IVA2 Clock activity status R 0x0
0x0: No domain clock activity
0x1: Domain clock is active
Table 3-114. Register Call Summary for Register CM_CLKSTST_IVA2
PRCM Basic Programming Model
• CM_CLKSTST_ <domain_name> (Clock State Status Register) : [0]
PRCM Register Manual
• IVA2_CM Register Summary : [1]
3.8.1.3 OCP_System_Reg_CM Registers
3.8.1.3.1 OCP_System_Reg_CM Register Summary
Table 3-115. OCP_System_Reg_CM Register Summary
Register Width
Register Name Type Address Offset Physical Address Reset Type
(Bits)
CM_REVISION R 32 0x0000 0000 0x4800 4800 C
CM_SYSCONFIG RW 32 0x0000 0010 0x4800 4810 W
3.8.1.3.2 OCP_System_Reg_CM Registers
Table 3-116. CM_REVISION
Address Offset 0x0000 0000
Physical Address 0x4800 4800 Instance OCP_System_Reg_CM
Description This register contains the IP revision code for the CM part of the PRCM
Type R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED REV
Bits Field Name Description Type Reset
31:8 RESERVED Reads returns 0. R 0x000000
7:0 REV IP revision R 0x10
[7:4] Major revision
[3:0] Minor revision
Examples: 0x10 for 1.0, 0x21 for 2.1
Table 3-117. Register Call Summary for Register CM_REVISION
PRCM Basic Programming Model
• Revision Information Registers : [0]
PRCM Register Manual
• OCP_System_Reg_CM Register Summary : [1]
466 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010
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