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PRCM Basic Programming Model
18. The PRM switches the I/O pad configuration only if the
[8] PAD_OFF_MODE_OVR
bit is set to 1; otherwise, the PAD configuration remains in off configuration until the software is
restored and clears this bit.
19. When the MPU reset time expires and pad configuration returns to normal mode, the MPU domain
reset is released.
20. When the MPU boots, the software accesses the control module to read the wake-up event source.
21. The software disables the I/O wake-up daisy chain by clearing the PRCM.
EN_IO bit and the PRCM.
[16] EN_IO_CHAIN bit.
3.5.7.4.2.2 Device Wakeup From Off Mode Using Only the SYS_OFF_MODE Signal
Depending on the external power IC capability and the user setting, VDD1 and VDD2 voltage control use
the direct sys_off_mode signal and do not send commands through the I
2
C interface.
in this case, the first part of the sequence in
is as follows.
Upon detection of a wakeup from the daisy chain, the PRM performs the following steps:
1. It enables the system clock oscillator and asserts sys_clkreq.
2. It ramps up the wake-up LDO.
3. It releases sys_off_mode.
4. It waits for the system clock oscillator setup time.
5. It waits for VDD1 and VDD2 setup time. The two counts are started in parallel.
6. When both timers expire, the following steps happen in parallel:
•
Reset is asserted on the MPU and CORE power domains.
•
The MPU and CORE power domains are powered up.
•
The PRM restarts the CORE and processor memory LDOs.
•
The PRM powers up all analog cells in the VDD1 and VDD2 domains.
3.6
PRCM Basic Programming Model
The PRCM module supports an extensive set of module-specific registers that allow programming control
over numerous features of the clocks, resets, and power-management signals for each power domain of
the device.
These registers are fully programmable and accessible by the MPU and the IVA2.2 subsystems.
Logically, the registers are grouped into five categories:
•
Global
•
Clock management
•
Reset management
•
Power management
•
Voltage management
3.6.1 Global Registers
3.6.1.1
Revision Information Registers
•
: Indicates the CM module revision code; it is read-only
•
: Indicates the PRM module revision code; it is read-only
3.6.1.2
PRCM Configuration Registers
•
: Holds an AUTOIDLE bit to control the CM internal clock autogating feature
•
: Holds an AUTOIDLE bit to control the PRM internal clock autogating feature
3.6.1.3
Interrupt Configuration Registers
The PRM can interrupt the MPU and the IVA2.2 subsystems as a result of four events:
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SWPU177N – December 2009 – Revised November 2010
Power, Reset, and Clock Management
Copyright © 2009–2010, Texas Instruments Incorporated