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SDRAM Controller (SDRC) Subsystem
Command
nCS
nRAS
nCAS
nWE
Autorefresh
L
L
L
H
•
Enter deep-power-down (CMDCODE: 0x3)
When the SDRC.
[3:0] CMDCODE field is programmed with 0x3, the SDRC
executes an enter DPDM command. This command is used for low-power devices (that is, LPSDR or
MDDR devices that support deep-power-down mode). The following table shows the status of the
SDRC memory port signals.
The device enters deep-power-down mode by having nCS and nWE held at logic low with nRAS and
nCAS high at the rising edge of the clock, while CKE is low.
Command
nCS
nRAS
nCAS
nWE
CKE
Enter DPDM
L
H
H
L
L
•
Exit deep-power-down command (CMDCODE: 0x4)
When the SDRC.
[3:0] CMDCODE field is programmed with 0x4, the SDRC
executes an exit deep-power-down command. The device exits deep-power-down mode when the
inhibit command is sampled with CKE held at logic high.
•
Enter self-refresh (CMDCODE: 0x5)
When the SDRC.
[3:0] CMDCODE field is programmed with 0x5, the SDRC puts the
memory into self-refresh. The signal status is the same as defined in autorefresh, and CKE is held at
logic low during the self-refresh entry command.
The self-refresh mode is entered from the all-banks-idle state by asserting nCS, nRAS, nCAS, and
CKE low, and nWE high.
Once the self-refresh mode is entered, only the CKE state being low matters; all other inputs, including
the clock, are ignored and remain in self-refresh mode.
•
Exit self-refresh (CMDCODE: 0x6)
When the SDRC.
[3:0] CMDCODE field is programmed with 0x6, the SDRC
executes the self-refresh exit command and, after meeting the tXSR timing parameter, executes one
autorefresh command to adhere to the memory protocol. It is an exit self-refresh command when CKE
is detected high with a NOP command.
Self-refresh is exited by restarting the external clock and then asserting CKE high. This must be
followed by NOPs for a minimum time of tXSR before the SDRAM reaches idle state to begin normal
operation.
•
Set the CKE signal high (CMDCODE: 0x7)
When the SDRC.
[3:0] CMDCODE field is programmed with 0x7, CKE is set to high.
An example of where this command is used is during DDR memory initialization.
•
Set the CKE signal low (CMDCODE: 0x8)
When the SDRC.
[3:0] CMDCODE field is programmed with 0x8, CKE is set to low.
An example of where this command can be used is to put memory in power-down mode.
10.2.5.4.1 Low-Power SDR/Mobile DDR Initialization Sequence
The initialization sequence is executed after the following occur:
1. Power is applied.
2. The clock is stable.
3. The power-on reset sequence is executed.
The initialization sequence is executed by programming the following manual command registers, in the
SDRC.
[3:0] CMDCODE bit field, on a per-CS basis:
1. Set CMDCODE to 0x0 (NOP command), for a minimum delay of 200
m
s. Another way to stabilize the
connected device internal circuits is to deactivate the corresponding CS for the same amount of time.
2273
SWPU177N – December 2009 – Revised November 2010
Memory Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated
