Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 3083 / 3738

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McBSP Integration
• McBSPi. MCBSPLP_WAKEUPEN_REG [0] RSYNCERREN bit: The McBSP module asserts the
McBSPi_SWAKEUP request when an unexpected receive frame-sync pulse is detected. If the
McBSPi.
MCBSPLP_IRQENABLE_REG [0] RSYNCERREN bit is set to 1, the McBSP module sends an
interrupt (McBSPi_IRQ) request o the MPU or IVA 2.2 subsystems when exiting from idle mode
(interrupt is asserted once the McBSPi.
MCBSPLP_IRQSTATUS_REG [0] RSYNCERR bit changes
from ‘0’ to ‘1’, indicating that a receive error occurred).
21.3.2.4.3.2 Transmit Wakeup
For transmit, there are also 5 possible wake-up configuration scenarios:
• McBSPi. MCBSPLP_WAKEUPEN_REG [14] XEMPTYEOFEN bit: The McBSP module asserts the
McBSPi_SWAKEUP request when a complete frame was transmitted and the transmit buffer is empty.
If the McBSPi.
MCBSPLP_IRQENABLE_REG [14] XEMPTYEOFEN bit is set to 1, the McBSP module
sends an interrupt (McBSPi_IRQ) request to the MPU or IVA 2.2 subsystems when exiting from idle
mode.
• McBSPi. MCBSPLP_WAKEUPEN_REG [10] XRDYEN bit: The McBSP module asserts the
McBSPi_SWAKEUP request when the transmit buffer reaches the high threshold value
(XTHRESHOLD value + 1) of the McBSPi.
MCBSPLP_THRSH2_REG register. If the
McBSPi. MCBSPLP_IRQENABLE_REG [10] XRDYEN bit is set to 1, the McBSP module sends an
interrupt (McBSPi_IRQ) request to the MPU or IVA 2.2 subsystems when exiting from idle mode
(interrupt is asserted once the McBSPi.
MCBSPLP_IRQSTATUS_REG [10] XRDY bit changes from ‘0’
to ‘1’, indicating that transmit buffer data is ready to accept new data).
• McBSPi. MCBSPLP_WAKEUPEN_REG [9] XEOFEN bit: The McBSP module asserts the
McBSPi_SWAKEUP request at the end of the frame. If the McBSPi. MCBSPLP_IRQENABLE_REG [9]
XEOFEN bit is set to 1, the McBSP module sends an interrupt (McBSPi_IRQ) request to the MPU or
IVA 2.2 subsystems when exiting from idle mode.
• McBSPi. MCBSPLP_WAKEUPEN_REG [8] XFSXEN bit: The McBSP module sends a
McBSPi_SWAKEUP request when a transmit frame-sync pulse is detected while the module is in idle
mode. If the McBSPi.
MCBSPLP_IRQENABLE_REG [8] XFSXEN bit is set to 1, the McBSP module
sends an interrupt (McBSPi_IRQ) request to the MPU or IVA 2.2 subsystems when exiting from idle
mode.
• McBSPi. MCBSPLP_WAKEUPEN_REG [7] XSYNCERREN bit: The McBSP module asserts the
McBSPi_SWAKEUP request when an unexpected transmits frame-sync pulse is detected. If the
McBSPi.
MCBSPLP_IRQENABLE_REG [7] XSYNCERREN bit is set to 1, the McBSP module sends an
interrupt (McBSPi_IRQ) request to the MPU or IVA 2.2 subsystems when exiting from idle mode
(interrupt will be asserted once the McBSPi.
MCBSPLP_IRQSTATUS_REG [7] XSYNCERR bit changes
from ‘0’ to ‘1’, indicating that a transmit error occurred).
21.3.2.4.3.3 Notes
When mcbsp1_fsr/mcbspi_fsx pins is configured as an output, the FSR/FSX wake-up generation makes
no sense (the module cannot be in Smart Idle mode).
Detection of RSYNCERR/XSYNCERR during idle mode can be used only when mcbsp1_fsr/mcbspi_fsx
pins is configured as an input and the remote system knows to assert such an error to trigger the wake up
of the McBSP module.
The module does not implement interrupt request (IRQ) assertion when configured as (GPIO). Pins that
can be used to accept input signals and/or send output signals but are not linked to specific uses); also a
wake up capability in this mode is not available.
21.3.2.4.4 Analysis of the Receiver Smart Idle Behavior
The analysis of the power mode behavior is shown in Table 21-6 :
In this table, the CLKRM bit is in the McBSPi. MCBSPLP_PCR_REG register on position 8, CLKXM bit in
the McBSPi. MCBSPLP_PCR_REG [9] register, and CLOCKACTIVITY bit in the
McBSPi. MCBSPLP_SYSCONFIG_REG [9:8] register.
The value X signifies that the bit value is not significant.
3083 SWPU177N – December 2009 – Revised November 2010 Multi-Channel Buffered Serial Port
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