Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 3087 / 3738

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McBSP Integration
Table 21-8. McBSP Common Interrupt Requests (continued)
Request Name Mapping Destination
McBSP5_IRQ IVA2_IRQ[37] IVA2.2 subsystem interrupt controller
M_IRQ_27 MPU subsystem interrupt controller
Table 21-9. McBSP Transmit Interrupt Requests
Request Name Mapping Destination
McBSP1_IRQ_TX IVA2_IRQ[16] IVA2.2 subsystem interrupt controller
M_IRQ_59 MPU subsystem interrupt controller
McBSP2_IRQ_TX IVA2_IRQ[19] IVA2.2 subsystem interrupt controller
M_IRQ_62 MPU subsystem interrupt controller
McBSP3_IRQ_TX IVA2_IRQ[21] IVA2.2 subsystem interrupt controller
M_IRQ_89 MPU subsystem interrupt controller
McBSP4_IRQ_TX IVA2_IRQ[23] IVA2.2 subsystem interrupt controller
M_IRQ_54 MPU subsystem interrupt controller
McBSP5_IRQ_TX IVA2_IRQ[25] IVA2.2 subsystem interrupt controller
M_IRQ_81 MPU subsystem interrupt controller
Table 21-10. McBSP Receive Interrupt Requests
Request Name Mapping Destination
McBSP1_IRQ_RX IVA2_IRQ[17] IVA2.2 subsystem interrupt controller
M_IRQ_60 MPU subsystem interrupt controller
McBSP2_IRQ_RX IVA2_IRQ[20] IVA2.2 subsystem interrupt controller
M_IRQ_63 MPU subsystem interrupt controller
McBSP3_IRQ_RX IVA2_IRQ[22] IVA2.2 subsystem interrupt controller
M_IRQ_90 MPU subsystem interrupt controller
McBSP4_IRQ_RX IVA2_IRQ[24] IVA2.2 subsystem interrupt controller
M_IRQ_55 MPU subsystem interrupt controller
McBSP5_IRQ_RX IVA2_IRQ[26] IVA2.2 subsystem interrupt controller
M_IRQ_82 MPU subsystem interrupt controller
An event can generate an interrupt request when the corresponding mask bit in the
McBSPi.
MCBSPLP_IRQENABLE_REG register is set to ‘1’.
Table 21-11 and Table 21-12 summarize the events causing the generation of an interrupt request.
Table 21-11. McBSP Transmit Interrupt Events
Event Name Status Bit Mask Bit Description
Transmit buffer McBSPi. MCBSPLP_IRQSTATUS_REG [14] McBSPi. MCBSPLP_IRQENABLE_REG This event happens when a
empty at end XEMPTYEOF [14] XEMPTYEOFEN complete frame was transmitted
of frame and the transmit buffer is empty .
Overflow McBSPi. MCBSPLP_IRQSTATUS_REG [12] McBSPi. MCBSPLP_IRQENABLE_REG This event happens when
XOVFLSTAT [12] XOVFLEN transmit data buffer is full and a
new data is written in this buffer.
The new data written is
discarded.
Underflow McBSPi. MCBSPLP_IRQSTATUS_REG [11] McBSPi. MCBSPLP_IRQENABLE_REG This event happens when
XUNDFLSTAT [11] XUNDFLEN transmit data buffer is empty and
a new data is required to be
transmitted.
Threshold McBSPi. MCBSPLP_IRQSTATUS_REG [10] McBSPi. MCBSPLP_IRQENABLE_REG This event happens when the
reached XRDY [10] XRDYEN transmit buffer free locations are
equal or above the
THRSH2_REG value.
End of Frame McBSPi. MCBSPLP_IRQSTATUS_REG [9] McBSPi. MCBSPLP_IRQENABLE_REG This event happens when a
XEOF [9] XEOFLEN complete frame was transmitted.
3087 SWPU177N – December 2009 – Revised November 2010 Multi-Channel Buffered Serial Port
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