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21.3.3 Hardware Requests
21.3.3.1 DMA Requests
The DMA requests are shared between the IVA2.2 subsystem DMA controller (eDMA) and system DMA
controller (sDMA). Each of the five McBSP modules can generate two DMA events:
•
McBSPi_DMA_TX : McBSPi module transmit request
•
McBSPi_DMA_RX : McBSPi module receive request
The following table summaries the DMA events with the mapping on both DMA controllers.
Table 21-7. McBSP DMA Requests
Request Name
Mapping
Destination
Description
McBSP1_DMA_TX
EDMA_REQ[0]
IVA2.2 subsystem DMA controller
write (or transmit) request
S_DMA_30
system DMA controller
McBSP1_DMA_RX
EDMA_REQ[1]
IVA2.2 subsystem DMA controller
read (or receive) request
S_DMA_31
system DMA controller
McBSP2_DMA_TX
EDMA_REQ[2]
IVA2.2 subsystem DMA controller
write (or transmit) request
S_DMA_32
system DMA controller
McBSP2_DMA_RX
EDMA_REQ[3]
IVA2.2 subsystem DMA controller
read (or receive) request
S_DMA_33
system DMA controller
McBSP3_DMA_TX
EDMA_REQ[4]
IVA2.2 subsystem DMA controller
write (or transmit) request
S_DMA_16
system DMA controller
McBSP3_DMA_RX
EDMA_REQ[5]
IVA2.2 subsystem DMA controller
read (or receive) request
S_DMA_17
system DMA controller
McBSP4_DMA_TX
EDMA_REQ[6]
IVA2.2 subsystem DMA controller
write (or transmit) request
S_DMA_18
system DMA controller
McBSP4_DMA_RX
EDMA_REQ[7]
IVA2.2 subsystem DMA controller
read (or receive) request
S_DMA_19
system DMA controller
McBSP5_DMA_TX
EDMA_REQ[8]
IVA2.2 subsystem DMA controller
write (or transmit) request
S_DMA_20
system DMA controller
McBSP5_DMA_RX
EDMA_REQ[9]
IVA2.2 subsystem DMA controller
read (or receive) request
S_DMA_21
system DMA controller
21.3.3.2 Interrupt Requests
21.3.3.2.1 McBSP Interrupt Requests
Each of the five McBSP modules can generate three interrupts, shared between the MPU subsystem and
IVA2.2 subsystem interrupt controllers:
•
McBSPi_IRQ: McBSPi module common interrupt request
•
McBSPi_IRQ_TX: McBSPi module transmit interrupt request
•
McBSPi_IRQ_RX: McBSPi module receive interrupt request
The following tables list the interrupt requests with the mapping.
Table 21-8. McBSP Common Interrupt Requests
Request Name
Mapping
Destination
McBSP1_IRQ
IVA2_IRQ[33]
IVA2.2 subsystem interrupt controller
M_IRQ_16
MPU subsystem interrupt controller
McBSP2_IRQ
IVA2_IRQ[34]
IVA2.2 subsystem interrupt controller
M_IRQ_17
MPU subsystem interrupt controller
McBSP3_IRQ
IVA2_IRQ[35]
IVA2.2 subsystem interrupt controller
M_IRQ_22
MPU subsystem interrupt controller
McBSP4_IRQ
IVA2_IRQ[36]
IVA2.2 subsystem interrupt controller
M_IRQ_23
MPU subsystem interrupt controller
3086
Multi-Channel Buffered Serial Port
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
