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Camera ISP Register Manual
Table 6-173. Register Call Summary for Register CCP2_LCx_CTRL (continued)
Camera ISP Basic Programming Model
•
Camera ISP CSI1/CCP2B Register Accessibility During Frame Processing
:
•
Camera ISP CSI1/CCP2B Enable/Disable the Hardware
•
Camera ISP CSI1/CCP2B Select the Mode: MIPI CSI1 or CCP2B
:
•
Camera ISP CSI1/CCP2B Video Port
•
Camera ISP CSI1/CCP2B Region of Interest
•
:
•
Camera ISP CSI1/CCP2B Destination Format
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Camera ISP CSI1/CCP2B Frame Acquisition
[22] [23] [24] [25] [26] [27] [28] [29]
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Camera ISP CSI1/CCP2B Pixel Data Region
Camera ISP Register Manual
•
Camera ISP CCP2 Register Summary
Table 6-174. CCP2_LCx_CODE
Address Offset
0x0000 0054 + (x * 0x30)
Index
x = 0 to 3
Physical Address
0x480B C454 + (x * 0x30)
Instance
ISP_CCP2
Description
CODE REGISTER - LOGICAL CHANNEL x. This register sets the codes that are used in the 32-bit
synchronization codes to recognize the logical channel, frame start, frame end, line start, and line end
codes. This register applies for logical channel x only. The default values should not be modified.
Updating this register with new codes under a flowing serial transmission on that channel causes
unexpected results.
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
CHAN_ID
FEC
FSC
LEC
LSC
Bits
Field Name
Description
Type
Reset
31:20
RESERVED
Write 0s for future compatibility. Read returns 0.
RW
0x000
19:16
CHAN_ID
Logical channel x identifier
RW
0x0 for LC0
The channel identifier is located between bits 4 to 7 in the
0x1 for LC1
32-bit synchronization codes.
0x2 for LC2
0x3 for LC3
15:12
FEC
Logical channel x frame end synchronization code
RW
0x3
identifier
The synchronization code identifier is between bits 0 to 3
in the 32-bit synchronization codes.
11:8
FSC
Logical channel x frame start synchronization code
RW
0x2
identifier
The synchronization code identifier is between bits 0 to 3
in the 32-bit synchronization codes.
7:4
LEC
Logical channel x line end synchronization code identifier
RW
0x1
The synchronization code identifier is between bits 0 to 3
in the 32-bit synchronization codes.
3:0
LSC
Logical channel x line start synchronization code identifier
RW
0x0
The synchronization code identifier is between bits 0 to 3
in the 32-bit synchronization codes.
Table 6-175. Register Call Summary for Register CCP2_LCx_CODE
Camera ISP Basic Programming Model
•
Camera ISP CSI1/CCP2B Register Accessibility During Frame Processing
:
•
Camera ISP CSI1/CCP2B Synchronization Codes
Camera ISP Register Manual
•
Camera ISP CCP2 Register Summary
1361
SWPU177N – December 2009 – Revised November 2010
Camera Image Signal Processor
Copyright © 2009–2010, Texas Instruments Incorporated