Texas Instruments OMAP36 Series, Technical Reference Manual

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camisp-200
PCLK
DATA[11:0]
DATA[11:0]
DAT0 DAT1 DAT2
DAT0 DAT1 DAT2
VP_CLK_POL=0x1
VP_CLK_POL=0x0
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Camera ISP Basic Programming Model
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– CCP2_CTRL [9:8] VP_OUT_CTRL
– The video-port output frequency varies from CAM_ICLK to CAM_ICLK/4 MHz. CAM_ICLK is the
CSI1/CCP2B receiver functional and interface clock. The reset value selects CAM_ICLK/2.
• CCP2_CTRL [11] VP_ONLY_EN:
– Controls whether the video-port output is the only output interface enabled and applies for all
channels.
– When CCP2_CTRL [11] VP_ONLY_EN = 0x1, the data are output only to the video port; the
interface master port is not used. The two parts of the frame (embedded data and pixel data) are
output to the video port (instead of pixel data to video port and embedded data to interconnect).
• The video port outputs the embedded data defined by the CCP2_LCx_STAT_START and
CCP2_LCx_STAT_SIZE registers without decompression.
• The video port outputs the pixel data defined by the CCP2_LCx_DAT_START and
CCP2_LCx_DAT_SIZE registers.
– The pixel data are decompressed according to the settings of the CCP2_LCx_CTRL [7:2] FORMAT
bit field. Table 6-59 summarizes the behavior of the video port as a function of the
CCP2_LCx_CTRL [7:2] FORMAT bit field.
Table 6-59. Camera ISP CSI1/CCP2B CCP2_LCx_CTRL[7:2] FORMAT and CCP2_CTRL[11]
VP_ONLY_EN = 1 Settings
CCP2_LCx_CTRL [7:2] Format Video-Port Behavior
VP or RAW8 + VP The incoming data are 8 bits. The pixel data are not compressed.
The embedded data are transmitted to the CCDC module on 8 bits (DATA[7:0]). The
pixel data are not decompressed.
The pixel data are transmitted to the CCDC module on 8 bits (DATA[7:0]).
RAW12 + VP The incoming data are 12 bits. The pixel data are not compressed.
The embedded data are transmitted to the CCDC module on 12 bits (DATA[11:0]). The
pixel data are reconstructed in the receiver.
The pixel data are transmitted to the CCDC module on 12 bits (DATA[11:0]). The pixel
data are not decompressed.
• Control the video-port pixel clock polarity:
– If CCP2_CTRL [12] VP_CLK_POL = 0x0, the CSI1/CCP2B receiver module writes the data on the
video port on the pixel-clock falling edge. The module connected to the VP samples the data on the
pixel clock rising edge.
– If CCP2_CTRL [12] VP_CLK_POL = 0x1, the CSI1/CCP2B receiver module writes the data on the
video port on the pixel-clock raising edge. The module connected to the VP samples the data on
the pixel clock falling edge.
Figure 6-105 shows the
CCP2_CTRL .VP_CLK_POL settings.
Figure 6-105. Camera ISP CSI1/CCP2B CCP2_CTRL.VP_CLK_POL Settings
6.5.3.11 Camera ISP CSI1/CCP2B Logical Channels
The CCP2B receiver supports simultaneous logical channels. Each logical channel is controlled
independently with its own set of registers. The four sets of registers are identical, but some reset values
are different.
The same description applies to all other logical channels. Logical channel LCx means LC0, LC1, LC2, or
LC3.
All the registers in this section can be modified at any time. However, the modifications apply only from
the start of the following frame.
1250 Camera Image Signal Processor SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated