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Display Subsystem Environment
NOTE:
In
,
, and
:
•
When HSync start and Hsync end short packets are not generated (HSA does not exist),
HBP signal must be different from 0.
•
The software must ensure that VBP is always defined so that there is at least one
HSYNC during VBP.
•
In blanking low-power mode (BL-LP), two options are possible
–
The lane remains in ULPS, and the
[20] BLANKING_MODE bit is set to
0x0.
–
Dummy bytes are sent during LP with the
[20] BLANKING_MODE bit set
to 0x1; the number of sent bytes is determined by the
[15:0]
BL_LP_INTERLEAVING bit field.
If the signal VP_DE is not asserted during enough VP_PCLK cycles to be able to capture the number of
bytes defined in the word count of the header, the module must send the valid data received on the video
port followed by bytes of 0s to match the required number of bytes to transmit. The VP_PCLK must be
present during all extra cycles where the DSI protocol engine is expecting pixels.
If the VP_DE signal is asserted for too many VP_PCLK cycles, the module should stop capturing the data
on the video port while the number of bytes to capture, as defined in the word count field of the header, is
reached.
The HS must check that the received synchronization events on the video port (VSYNC and HSYNC) are
within the synchronization window based on expected timings. If the timings (internal and received) are
out of sync, the interrupt for out-of-sync must be generated and the interface must be disabled
(DSS.
[0] IF_EN bit is automatically reset by hardware). The unsynchronization window is
defined by the DSS.
[27:24] WINDOW_SYNC bit field.
7.2.2.2.2 Video Port Used on Command Mode
If the video port is used for command mode, the VP_HSYNC, VP_VSYNC, and VP_DE signals are not
used.
describes the active signals on the video port.
Table 7-12. Video Interface in the Context of Command Mode
Signal Name
Type
(1)
Description
VP_DATA[23:0]
I
Parallel output data: bits 0 to 23
VP_PCLK
I
One pulse is generated every time new data is output on the data bus
VP_STALL
O
The stall signal must be deasserted to receive pixel and asserted to stop
receiving pixel. (It can be used only while the display controller is configured in
STALL mode; in that mode, HSYNC and VSYNC are not generated).
VP_CLK
I
Display controller internal clock: It is a free running clock used as the display
controller functional clock. The maximum frequency is 173 MHz at nominal
voltage and 96 MHz at low voltage.
(1)
I = Input, O = Output
NOTE:
The stall signal must be deasserted to receive pixels and asserted to stop receiving pixels.
and
show the VP_STALL signal assertion and deassertion on rising and falling
edges, respectively.
NOTE:
In DSI command mode, the display controller must be configured in stall mode by setting
the DSS.
[11] STALLMODE bit to 1.
1593
SWPU177N – December 2009 – Revised November 2010
Display Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated
