VP_CLK
VP_PCLK
VP_STALL
VP_DATA[23:0]
ALWAYS_1_period_of_VP.CLK
1_VP.CLK_cycles_after_rising_edge_pclk
4_VP.CLK_cycles_for_assertion
PIXELS #1
PIXELS #2
PIXELS #3
PIXELS #4
PIXELS #5
dss-187
VP_CLK
VP_PCLK
VP_STALL
VP_DATA[23:0]
ALWAYS_1_period_of_VP.CLK
1_VP.CLK_cycles_after_for_de-assertion
4_VP.CLK_cycles_for_assertion
PIXELS #1
PIXELS #2
PIXELS #3
PIXELS #4
PIXELS #5
dss-188
Public Version
Display Subsystem Environment
www.ti.com
Figure 7-37. Stall Timing With Pixel on Rising Edge
Figure 7-38. Stall Timing With Pixel on Falling Edge
To stop the transfer, the VP_STALL signal must be asserted when the last data is output. The data can be
output on the rising or falling edge of the VP_PCLK through registers in the display controller module. The
case with data output on falling edge of VP_PCLK is supported by the DSI protocol engine.
The VP_PCLK clock is generated from VP_CLK; these two clocks are balanced. Assertion and
deassertion of VP_PCLK is done on the rising edge of VP_CLK. The width of the VP_PCLK pulse
depends on the configuration of the clock divisor in the display controller (DSS.
[7:0] PCD
bit field). In the DSI protocol engine, the information is defined in the DSS.
[4] VP_CLK_RATIO
bit and must be aligned with the display controller configuration.
Deassertion of the VP_STALL signal must occur at least 4 VP_CLK cycles before assertion of VP_PCLK.
Assertion of VP_STALL must occur one cycle VP_CLK after deassertion of VP_PCLK for the last pixel to
be transferred. The VP_CLK clock is generated by the display controller under software control. It can be
kept running between assertion and deassertion of VP_STALL.
The word count (WC) defined in the DSS.
register for the virtual
channel (VC)associated with the video port, indicates the number of bytes to receive (one line or two lines
can be used, depending on the WC and size of the line buffer). The total size defined in the WC of the
header register cannot exceed the size of the line buffer multiplied by the number of buffer lines.
The stall assertion/deassertion depends on the number of bytes to be received considering the size of the
video port bus defined in the DSS.
[7:6] VP_DATA_BUS_WIDTH bit field.
shows the data flow in command mode using the video port.
1594
Display Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated