Public Version
Display Subsystem Functional Description
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Active Matrix Technology: The encoded pixel values are used by spatial/temporal dithering logic to
display the data in a lower color depth on the LCD panel. The spatial/temporal dithering algorithm is
based on the (x,y) pixel position, the value of removed bits and the frame number. The picture quality
is improved when enabling the spatial/temporal dithering logic. When spatial/temporal dithering is not
enabled, the three MSBs of the pixel color components are output on the interface data bus if the
interface data bus is smaller than the pixel format size. If the interface data bus is wider than the pixel
format size, by programming the pixel components replication active/inactive, the MSB is replicated to
the LSB of the interface data bus or the LSB is filled with 0s.
7.4.2.5.2 Passive Matrix Display Dithering Logic
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Passive matrix technology
After the graphics data are merged with the video data from the video layers depending on the
transparency status, the result is sent to the color/grayscale space-/time-based dither generator. The
monochrome data and each RGB color component are encoded on 4 bits, which are the 4 MSBs of
the pixel-encoded component 8-bit value defined by the merge of the graphics data and the video data.
These 4-bit values are used to select on the 16 intensity levels. The gray/color intensity is controlled by
turning individual pixels on and off at varying period rates, making the average time the pixel is off
longer than the average time the pixel is on, thus producing more intense grays/colors. The dithering
generator also uses the intensity of adjacent pixels in the calculation to give the screen image a
smooth appearance. The proprietary dither algorithm is optimized to provide a range of intensity values
that matches the visual perception of color/gray graduations.
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Active matrix technology
The passive matrix dithering logic is always bypassed in active displays.
NOTE:
If the interface data bus is smaller than the pixel format size, dithering logic can be enabled.
If the interface data bus is wider than the pixel format size, the dithering logic cannot be
enabled and replication feature can be used.
7.4.2.5.3 Passive Matrix Display Output FIFO
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Passive matrix technology
The display controller contains a 2-entry by 8-bit-wide output FIFO used to store pixel data before it is
driven out to the LCD pins. Each time a modulated pixel value is output from the dither generator, it is
placed into a serial shifter. The shifter can be configured to be 4 or 8 bits wide. Single-panel
monochrome screens use either four or eight data lines; single-panel color screens use eight data
pins.
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Active matrix technology
The output FIFO is bypassed in active matrix mode.
7.4.2.5.4 Multiple Cycle Output Format
The pixels after the active matrix display processing are formatted on one or multiple cycles (from one to
three cycles). The interface width can be 8-, 9-, 12-, or 16-bit. On three cycles, two pixels can concatenate
and send to the panel. When the TDM is disabled, the display controller outputs the pixels using the
conventional formats: Passive matrix display/active matrix display monochrome/color.
The following example shows an output configuration based on the interface width (8-bit) and the pixel
format output (24-bit) (also see
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The DSS.
[24:23] TDMCYCLEFORMAT bit field is set to 0x2 (three cycles for one
pixel).
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The DSS.
(k=0) register is set to 0x00000008 (8 bits from pixel 1 for the first
cycle).
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The DSS.
(k=1) register is set to 0x00000008 (8 bits from pixel 1 for the
second cycle).
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The DSS.
(k=2) register is set to 0x00000008 (8 bits from pixel 1 for the third
cycle).
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Display Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated