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Display Subsystem Environment
7.2.1.1
Parallel Interface
In parallel interface, the paths of the display subsystem modules are the display controller and the RFBI.
The display controller provides the required control signals to interface the memory frame buffer (SDRAM
or SRAM) directly to the external displays. The display controller is connected to the memory through the
L3 interconnect and has its own DMA (with embedded FIFOs) to read data from the system memory. The
L3 interconnect is the master port, while the L4 interconnect is the slave port of the display subsystem.
The display controller has two I/O pad modes at the module level:
•
RFBI mode (RFBI enabled), which implements the MIPI DBI 2.0 protocol
•
Bypass mode (RFBI disabled), which implements the MIPI DPI 1.0 protocol
The DSS.
[16:15] GPOUT[1:0] bits control selection of the display subsystem modules
(see
).
Table 7-2. I/O Pad Mode Selection
DSS.
[16] GPOUT1
DSS.
[15] GPOUT0
Mode
0
0
Reset
0
1
RFBI mode
1
0
Invalid
1
1
Bypass mode
The RFB of the LCD panel is connected directly to the RFBI module of the device. The RFBI controls the
reads/writes from/to the RFB. The RFBI receives the output from the DISPC (which takes data from the
memory) and generates the signals to control the LCD panel. Through the RFBI, the MPU can send
commands or parameter/display data to the LCD panel and directly set the DISPC registers to read/write
the data from/to the memory in the LCD panel. The RFBI can manage up to two LCD panels when the
serial interface is not used.
7.2.1.1.1 Parallel Interface in RFBI Mode (MIPI DBI Protocol)
shows the LCD support parallel interface in RFBI mode (example for 16-bit data interface).
1569
SWPU177N – December 2009 – Revised November 2010
Display Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated
