NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 1664 / 1761

Note that the received frame's Identifier field is always stored in the matching mailbox,
thus the contents of the ID field in a mailbox may change if the match was due to
masking. When MCR[SRXDIS] is asserted, FlexCAN will not store frames transmitted
by itself in any MB, even if it contains a matching Rx mailbox, and no interrupt flag or
interrupt signal will be generated. Otherwise, when MCR[SRXDIS] is deasserted,
FlexCAN can receive frames transmitted by itself if a matching Rx mailbox exists.
To be able to receive CAN frames through the Rx FIFO, the CPU must enable and
configure the Rx FIFO during Freeze mode (see
Rx FIFO ). Upon receiving the Frames
Available in Rx FIFO interrupt (see the description of IFLAG1[BUF5I] "Frames
available in Rx FIFO"), the CPU should service the received frame using the following
procedure:
1. Read the Control and Status word (optional: needed only if a mask was used for IDE
and RTR bits).
2. Read the ID field (optional: needed only if a mask was used).
3. Read the data field.
4. Read the RXFIR register (optional).
5. Clear the Frames Available in Rx FIFO interrupt by writing one to IFLAG1[BUF5I]
(mandatory: releases the MB and allows the CPU to read the next Rx FIFO entry).
When MCR[DMA] is asserted, upon receiving a frame in FIFO, IFLAG1[BUF5I]
generates a DMA request and does not generate a CPU interrupt (see
Rx FIFO under
DMA operation ). The IMASK1 bits in Rx FIFO region are not used.
The DMA controller must service the received frame using the following procedure:
1. Read the Control and Status word (read 0x80 address, optional).
2. Read the ID field (read 0x84 address, optional).
3. Read all data bytes (start read at 0x88 address, optional).
4. Read the last data bytes (read 0x8C address is mandatory).
49.5.4 Matching process
The matching process scans the MB memory looking for Rx MBs programmed with the
same ID as the one received from the CAN bus. If the FIFO is enabled, the priority of
scanning can be selected between mailboxes and FIFO filters. The matching starts from
the lowest number message buffer toward the higher ones. If no match is found within the
first structure then the other is scanned subsequently. In the event that the FIFO is full,
the matching algorithm always looks for a matching MB outside the FIFO region.
For Rx FIFO see Rx FIFO .
Functional description
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
1664 NXP Semiconductors