NXP Semiconductors MWCT101 S Series, Reference Manual

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Table 26-3. SCG modes of operation (continued)
Mode Description
In FIRC mode, SCGCLKOUT and system clocks are derived from the fast internal reference clock.
Four frequency range settings are available for FIRC clock as described in the FIRC[RANGE]
register definition. Changes to FIRC range settings will be ignored when FIRC clock is enabled.
Sys PLL (SPLL) Sys PLL (SPLL) mode is entered when all the following conditions occur:
• RUN MODE: 0110 is written to RCCR[SCS].
HSRUN MODE: 0110 is written to HCCR[SCS].
• SPLLEN = 1
• SPLLVLD = 1
In SPLL mode, the SCGCLKOUT and system clocks are derived from the output of PLL which is
controlled by the System Oscillator (SOSC) clock. The selected PLL clock frequency locks to a
multiplication factor, as specified by its corresponding SCG_SPLLCFG[MULT], times the selected
PLL reference frequency. The PLL's programmable reference divider must be configured to produce
a valid PLL reference clock. This divide value is defined by the SCG_SPLLCFG[PREDIV] bits.
Stop Entered whenever the MCU enters a Stop state. The power modes are chip specific. For power
mode assignments, see the chapter that describes how modules are configured and SCG behaviour
during Stop recovery. Entering Stop mode, all SCG clock signals are static except the following
clocks which can continue to run and stay enabled in the following cases:
SIRCCLK is available in Normal Stop and VLPS mode when all the following conditions become
true:
• SIRCCSR[SIRCEN] = 1
• SIRCCSR[SIRCSTEN] = 1
• SIRCCSR[SIRCLPEN] = 1 in VLPS
Functional description
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
564 NXP Semiconductors