NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 308 / 1761

16.4.5.3.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R VLD 0 ECX
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 CPE 0 ERRCHN SAE SOE DAE DOE NCE SGE SBE DBE
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16.4.5.3.4 Fields
Field Function
31
VLD
VLD
Logical OR of all ERR status bits
0b - No ERR bits are set.
1b - At least one ERR bit is set indicating a valid error exists that has not been cleared.
30-17
—
Reserved
16
ECX
Transfer Canceled
0b - No canceled transfers
1b - The last recorded entry was a canceled transfer by the error cancel transfer input
15
—
Reserved
14
CPE
Channel Priority Error
0b - No channel priority error
1b - The last recorded error was a configuration error in the channel priorities . Channel priorities
are not unique.
13-12
—
Reserved
11-8
ERRCHN
Error Channel Number or Canceled Channel Number
The channel number of the last recorded error, excluding CPE errors, or last recorded error canceled
transfer.
7
SAE
Source Address Error
0b - No source address configuration error.
1b - The last recorded error was a configuration error detected in the TCDn_SADDR field.
TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].
6
SOE
Source Offset Error
0b - No source offset configuration error
1b - The last recorded error was a configuration error detected in the TCDn_SOFF field.
TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].
5
DAE
Destination Address Error
0b - No destination address configuration error
Table continues on the next page...
Memory map/register definition
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
308 NXP Semiconductors