NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 1178 / 1761

41.4.3.26.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0 0
GLE N
LDOK
HCSE L
CH7SE L CH6SE L CH5SE L CH4SE L CH3SE L CH2SE L CH1SE L CH0SE L
W
GLDOK
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
41.4.3.26.4 Fields
Field Function
31-12
—
Reserved
11
GLDOK
Global Load OK
This bit controls the global load mechanism. It generates a pulse at FTM module global load output with
one FTM clock cycle width, which is used to set LDOK bits of FTM and other modules (including other
FTMs). This bit is self-cleared and read value is always zero.
The global load mechanism depends on SoC specific information. Refer to FTM SoC specific information
to more details.
0b - No action.
1b - LDOK bit is set.
10
GLEN
Global Load Enable
This bit enables the global load mechanism implemented by GLDOK. If GLEN bit is set, then an external
event on the FTM global load input sets the LDOK bit. The clear of the LDOK bit is done by CPU writes '0'
to the bit.
0b - Global Load Ok disabled.
1b - Global Load OK enabled. A pulse event on the module global load input sets the LDOK bit.
9
LDOK
Load Enable
Enables the loading of the MOD, CNTIN, HCR and CV registers with the values of their buffers.
The LDOK bit can also be set by the Global Load mechanism if GLEN bit is enabled.
0b - Loading updated values is disabled.
1b - Loading updated values is enabled.
8
HCSEL
Half Cycle Select
This bit enables the half cycle match as a reload oportunity. A half cycle is defined by when the FTM
counter matches the HCR register.
0b - Half cycle reload is disabled and it is not considered as a reload opportunity.
1b - Half cycle reload is enabled and it is considered as a reload opportunity.
Table continues on the next page...
Memory map and register definition
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
1178 NXP Semiconductors