NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 1289 / 1761

NOTE
It is recommended to use only one PWM Edge Dithering
(channel (n) PWM Edge Dithering or channel (n+1) PWM
Edge Dithering) at a time.
For the generation of 0% PWM in the channel (n) (with channel
(n) ELSB:ELSA = 2'b10) using Modified Combine PWM mode
and PWM Edge Dithering, it is recommended to use:
• (C(n)V < CNTIN or C(n)V > MOD) and (channel (n)
FRACVAL is zero) and
• (CNTIN ≤ C(n+1)V ≤ MOD) and (channel (n+1)
FRACVAL is zero).
For the generation of 100% PWM in the channel (n) (with
channel (n) ELSB:ELSA = 2'b10) using Modified Combine
PWM mode and PWM Edge Dithering, it is recommended to
use:
• (CNTIN ≤ C(n)V ≤ MOD) and (channel (n) FRACVAL is
zero) and
• (C(n+1)V < CNTIN or C(n+1)V > MOD) and (channel (n
+1) FRACVAL is zero).
41.6 Reset Overview
The FTM is reset whenever any chip reset occurs.
When the FTM exits from reset:
• the FTM counter and the prescaler counter are zero and are stopped (CLKS[1:0] =
2'b00);
• the timer overflow interrupt is zero ( Timer Overflow Interrupt );
• the channels interrupts are zero ( Channel (n) Interrupt );
• the fault interrupt is zero ( Fault Interrupt );
• the channels are in input capture mode ( Input Capture Mode );
• the channels outputs are zero;
• the channels ELSB:ELSA = 0:0 (
Channel Modes ) and PWMEN = 0 ( External
Control of Channels Output ).
The following figure shows the FTM behavior after the reset. At the reset (item 1), the
FTM counter is disabled (CLKS[1:0] = 2'b00), its value is updated to zero and the pins
are not controlled by FTM (
Channel Modes ).
Chapter 41 FlexTimer Module (FTM)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 1289