NXP Semiconductors MWCT101 S Series, Reference Manual

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Field Function
0b - Transfers will stall when the transmit FIFO is empty or the receive FIFO is full
1b - Transfers will not stall, allowing transmit FIFO underruns or receive FIFO overruns to occur
2
AUTOPCS
Automatic PCS
For correct operations, the LPSPI slave normally requires the PCS to negate between frames. Setting the
Automatic PCS bit will cause the LPSPI to generate an internal PCS signal at the end of each transfer
word when the Clock Phase bit TCR[CPHA] = 1.
• When the Automatic PCS bit is set, the SCK must remain idle for at least 4 LPSPI functional clock
cycles (divided by the Prescaler Value TCR[PRESCALE] configuration) between each word, to
ensure correct operations
• In master mode, the Automatic PCS bit is ignored
0b - Automatic PCS generation is disabled
1b - Automatic PCS generation is enabled
1
SAMPLE
Sample Point
When set, the LPSPI master will sample the input data on a delayed LPSPI_SCK edge, which improves
the setup time when sampling data.
• The input data setup time in master mode with delayed LPSPI_SCK edge is equal to the input data
setup time in slave mode
• In slave mode, the SAMPLE bit is ignored
0b - Input data is sampled on SCK edge
1b - Input data is sampled on delayed SCK edge
0
MASTER
Master Mode
Configures the LPSPI in master or slave mode. The Master Mode bit directly controls the direction of the
LPSPI_SCK and LPCPI_PCS pins.
0b - Slave mode
1b - Master mode
45.3.1.10 Data Match Register 0 (DMR0)
45.3.1.10.1 Offset
Register Offset
DMR0 30h
Memory Map and Registers
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
1386 NXP Semiconductors