NXP Semiconductors MWCT101 S Series, Reference Manual

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However, if there was the overflow of the channel (n) accumulator in the current CPWM
period, then the initial edge of CPWM duty cycle happens when (FTM counter = C(n)V
+ 0x0001) and the FTM counter is decrementing, and the final edge of CPWM duty cycle
when (FTM counter = C(n)V + 0x0001) and the FTM counter is incrementing.
The following figure shows an example of PWM edge dithering when the channel (n) is
in CPWM mode.
5 4 3 2 1 0 1 2 3 4 5 6 5 4 3 2 1 0 1 2 3 4 5 6 5 4
channel (n) output
FTM counter
accumulator
0x1B 0x1E
overflow
0x01
2 3
channel (n) is in CPWM with high-true pulses
channel (n) ELSB:ELSA = 2'b10
CNTIN = 0x0000
MOD = 0x0006
C(n)V = 0x0003
channel (n) FRACVAL = 0x03
T is the period of one unit of FTM counter
6 5 4
CPWM duty cycle DC1 =
2 x (C(n)V - CNTIN) x T =
0x0006 x T
1 0 1 2 3 4 5 6 5 4 3 2 1 0
CPWM duty cycle DC2 =
2 x (C(n)V - CNTIN + 0x0001) x T =
0x0008 x T
dithering (one unit of
FTM counter)
0x04
0x07
dithering (one unit of
FTM counter)
CPWM duty cycle DC1 =
2 x (C(n)V - CNTIN) x T =
0x0006 x T
Figure 41-122. Channel (n) is in CPWM Mode with PWM Edge Dithering
41.5.34.2.3 Combine Mode
In the Combine mode, the PWM edge dithering can be done:
• in the channel (n) match (FTM counter = C(n)V) edge or
• in the channel (n+1) match (FTM counter = C(n+1)V) edge.
The channel (n) match edge dithering is enabled when a non-zero value is written to the
channel (n) FRACVAL.
For the channel (n) match edge dithering, the channel (n) has an internal 5-bit
accumulator. At the end of each PWM period, the channel (n) FRACVAL value is added
to the channel (n) accumulator. When this accumulator overflows (that is, the result of the
adding is greater or equal than 0x20), the accumulator remains with the rest of the
subtraction: (the result of this adding - 0x20).
If there was not the overflow of the channel (n) accumulator in the current PWM period,
the channel (n) match edge is not modified, that is, it happens on channel (n) match.
However, if there was the overflow of the channel (n) accumulator, the channel (n) match
edge happens when (FTM counter = C(n)V + 0x0001).
The following figure shows an example of the channel (n) match edge dithering when the
channels (n) and (n+1) are in Combine mode.
Chapter 41 FlexTimer Module (FTM)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 1285