NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 1606 / 1761

49.4.2.13 Error and Status 2 register (ESR2)
49.4.2.13.1 Offset
Register Offset
ESR2 38h
49.4.2.13.2 Function
This register reports some general status information.
49.4.2.13.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 LPTM
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 VPS IMB 0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
49.4.2.13.4 Fields
Field Function
31-23
—
Reserved
22-16
LPTM
Lowest Priority Tx Mailbox
If ESR2[VPS] is asserted, this field indicates the lowest number inactive mailbox (see the ESR2[IMB] bit
description). If there is no inactive mailbox then the mailbox indicated depends on the value of
CTRL1[LBUF]. If CTRL1[LBUF] is negated, then the mailbox indicated is the one that has the greatest
arbitration value (see
Highest-priority mailbox first ). If CTRL1[LBUF] is asserted then the mailbox
indicated is the highest number active Tx mailbox. If a Tx mailbox is being transmitted it is not considered
in LPTM calculation. If ESR2[IMB] is not asserted and a frame is transmitted successfully, LPTM is
updated with its mailbox number.
15
—
Reserved
14 Valid Priority Status
Table continues on the next page...
Memory map/register definition
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
1606 NXP Semiconductors