NXP Semiconductors MWCT101 S Series, Reference Manual

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DATA and/or CRC DLC EOF
Interm
Matching Window (26 to 90 CAN bits)
Move-in
Window
Start Move
(bit 2)
Figure 49-9. Matching and move-in time windows
CRC EOF
Interm
Arbitration Window (25 CAN bits)
Move-out
Window
Start Move
(bit 1)
Arb
Process
Start Arbitration
(delayed by TASD)
Figure 49-10. Arbitration and move-out time windows
BusOff
Internal Counter
counting 128 occurrences of 11 recessive CAN bits
128 126 125
Arb
Process
TASD
Count Move-out
Window
124 123
... ...
3 2 1 0
Figure 49-11. Arbitration at the end of bus off and move-out time windows
NOTE
In the preceding figures, the matching and arbitration timing
does not take into account the delay caused by the concurrent
memory access due to the CPU or other internal FlexCAN
subblocks.
49.5.9.9 Tx arbitration start delay
CTRL2[TASD] (Tx Arbitration Start Delay) is a variable that indicates the number of
CAN bits used by FlexCAN to delay the Tx arbitration process start point from the first
bit of CRC field of the current frame. This variable can be written only in Freeze mode
because it is blocked by hardware in other modes.
The transmission performance is impacted by the ability of the CPU to reconfigure
message buffers (MBs) for transmission after the end of the internal arbitration process,
where FlexCAN finds the winner MB for transmission (see
Arbitration process ). If the
Chapter 49 FlexCAN
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 1697