NXP Semiconductors MWCT101 S Series, Reference Manual

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b. Clock monitors (SOSCCSR[SOSCCME] and SPLLCSR[SPLLCME]) and their
corresponding reset events monitors (SOSCCSR[SOSCCMRE] and
SPLLCSR[SPLLCMRE]) are enabled for SOSC/SPLL
c. SOSC/SPLL is selected as system clock source
2. SOSC/SPLL clock monitor disable sequence requirement: Ensure below
sequence for disabling clock monitors while switching system clock source from
SOSC/SPLL:
a. System clock source switched from SOSC/SPLL
b. Disable Clock monitors (SOSCCSR[SOSCCME] and SPLLCSR[SPLLCME])
and their corresponding reset event monitors (SOSCCSR[SOSCCMRE] and
SPLLCSR[SPLLCMRE]) for SOSC/SPLL
It is imperative to follow the above guidelines to safeguard the device operation
against loss of clock scenarios if system clock source malfunction due to any reason.
26.2 Introduction
The system clock generator (SCG) module provides the system clocks of the MCU. The
SCG contains a system phase-locked loop (SPLL), a slow internal reference clock
(SIRC), a fast internal reference clock (FIRC), and the system oscillator clock (SOSC).
The SPLL is sourced by the SOSC reference clock. The SCG can select either the output
clock of the SPLL or a SCG reference clock (SIRC, FIRC, and SOSC) as the source for
the MCU system clocks. The SCG also supports operation with crystal oscillators, which
allows an external crystal, ceramic resonator, or another external clock source to produce
the external reference clock (which are also available as clock sources for the MCU
systems clocks).
26.2.1 Features
Key features of the SCG module are:
• System Phase-locked loop (SPLL):
• Voltage-controlled oscillator (VCO)
• External reference clock is used as the PLL source
• Modulo VCO frequency divider
• Phase/Frequency detector
• Integrated loop filter
Chapter 26 System Clock Generator (SCG)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 531