NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 1583 / 1761

Field Function
NOTE: In this mode, MCR[SRXDIS] cannot be asserted because this will impede the self-reception of a
transmitted message.
NOTE: FDCTRL[TDCEN] must be disabled when LPB is asserted.
0b - Loop Back disabled.
1b - Loop Back enabled.
11
TWRNMSK
Tx Warning Interrupt Mask
This bit provides a mask for the Tx Warning interrupt associated with the TWRNINT flag in the Error and
Status Register 1 (ESR1). This bit is read as zero when MCR[WRNEN] is negated. This bit can be written
only if MCR[WRNEN] is asserted.
0b - Tx Warning interrupt disabled.
1b - Tx Warning interrupt enabled.
10
RWRNMSK
Rx Warning Interrupt Mask
This bit provides a mask for the Rx Warning interrupt associated with the RWRNINT flag in the Error and
Status Register 1 (ESR1). This bit is read as zero when MCR[WRNEN] bit is negated. This bit can be
written only if MCR[WRNEN] bit is asserted.
0b - Rx Warning interrupt disabled.
1b - Rx Warning interrupt enabled.
9
—
Reserved
8
—
Reserved
7
SMP
CAN Bit Sampling
This bit defines the sampling mode of CAN bits at the Rx input. It can be written in Freeze mode only,
because it is blocked by hardware in other modes.
NOTE: For proper operation, to assert SMP it is necessary to guarantee a minimum value of two TQs in
CTRL1[PSEG1] (or CBT[EPSEG1]).This bit cannot be asserted when CAN FD is enabled
(MCR[FDEN] = 1).
0b - Just one sample is used to determine the bit value.
1b - Three samples are used to determine the value of the received bit: the regular one (sample
point) and two preceding samples; a majority rule is used.
6
BOFFREC
Bus Off Recovery
This bit defines how FlexCAN recovers from Bus Off state. If this bit is negated, automatic recovering
from Bus Off state occurs according to the CAN Specification 2.0B. If the bit is asserted, automatic
recovering from Bus Off is disabled and the module remains in Bus Off state until the bit is negated by the
user. If the negation occurs before 128 sequences of 11 recessive bits are detected on the CAN bus,
then Bus Off recovery happens as if the BOFFREC bit had never been asserted. If the negation occurs
after 128 sequences of 11 recessive bits occurred, then FlexCAN will resynchronize to the bus by waiting
for 11 recessive bits before joining the bus. After negation, the BOFFREC bit can be reasserted again
during Bus Off, but it will be effective only the next time the module enters Bus Off. If BOFFREC was
negated when the module entered Bus Off, asserting it during Bus Off will not be effective for the current
Bus Off recovery.
NOTE: See Bus off in the CAN Protocol standard (ISO 11898-1) for details.
0b - Automatic recovering from Bus Off state enabled.
1b - Automatic recovering from Bus Off state disabled.
5
TSYN
Timer Sync
This bit enables a mechanism that resets the free running timer each time a message is received in
message buffer 0. This feature provides means to synchronize multiple FlexCAN stations with a special
“SYNC” message, that is, global network time. If MCR[RFEN] is set (Rx FIFO enabled), the first available
mailbox, according to CTRL2[RFFN] setting, is used for timer synchronization instead of MB0. This bit
can be written in Freeze mode only because it is blocked by hardware in other modes.
Table continues on the next page...
Chapter 49 FlexCAN
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 1583