NXP Semiconductors MWCT101 S Series, Reference Manual

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42.5.1 LPIT programming model
Low Power Periodic Interrupt Timer (LPIT)
32/16-bit Counter
Module Control
MCR[...]
Module Status
MSR[...]
Version ID
VERID[...]
Parameter
PARAM[...]
Module Interrupt Enable
MIER[...]
Set Timer Enable
SETTEN[...]
Clear Timer Enable
CLRTEN[...]
Timer Value
TVALn[...]
Current Timer
CVALn[...]
Value
Timer Control
TCTRLn[...]
Number of timers
Number of external
Debug mode
Doze mode
Timer interrupt
flags
Timer interrupt
enables
Timer enables
Disable timers
by clearing
Compare modes:
Timeout period
Counter modes
Chaining channels
Programming Model
trigger inputs
Module clock
Software reset
timer enables
Capture modes:
Timer value when
trigger is asserted
Select Trigger
Select Trigger sources
Timer enables
Timer Reload on Trigger
Timer Stop on Interrupt
Timer Start on Trigger
Device
Identifiers
or Trigger Accumulator
or Trigger Input Capture
1 2
3
4
5
Load a
Read
starting
value
Timer Enable T_EN
Sets T_EN bit
in Timer Control Register
Interrupt Enable
TIE_ n
Channel n Timer
Channel registers must
be set for each channel
Global registers
must
only be set once
Figure 42-4. Programming Model
Global registers need only be set once:
• Version ID Register (VERID)
• Parameter Register (PARAM)
• Module Control Register (MCR)
• Module Status Register (MSR)
• Module Interrupt Enable Register (MIER)
• Set Timer Enable Register (SETTEN)
• Clear Timer Enable Register (CLRTEN)
Channel registers must be set for each channel:
• Timer Value Register (TVAL0 - TVAL3)
Functional description
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
1318 NXP Semiconductors