NXP Semiconductors MWCT101 S Series, Reference Manual, Page: 1574 / 1761

Table 49-5. Register access and reset information (continued)
Register Access type
Affected by
hard reset
Affected by
soft reset
Pretended Networking Payload High Filter 2 Register / Payload High Mask
Register (PL2_PLMASK_HI)
S/U Yes Yes
Pretended Networking Wake Up Message Buffer 0 register (WMB0) S/U Yes No
Pretended Networking Wake Up Message Buffer 1 register (WMB1) S/U Yes No
Pretended Networking Wake Up Message Buffer 2 register (WMB2) S/U Yes No
Pretended Networking Wake Up Message Buffer 3 register (WMB3) S/U Yes No
CAN FD Control register (FDCTRL) S/U Yes No
CAN FD Bit Timing register (FDCBT) S/U Yes No
CAN FD CRC register (FDCRC) S/U Yes Yes
The FlexCAN module can store CAN messages for transmission and reception using
mailboxes and Rx FIFO structures.
49.4.2 CAN register descriptions
The table below shows the FlexCAN memory map.
The address range from offset 0x80 to 0x27F allocates the thirty-two 128-bit message
buffers (MBs).
The memory maps for the message buffers are in FlexCAN message buffer memory map .
49.4.2.1 CAN memory map
FlexCAN0 base address: 4002_4000h
FlexCAN1 base address: 4002_5000h
FlexCAN2 base address: 4002_B000h
Offset Register Width
(In bits)
Access Reset value
0h Module Configuration register (MCR) 32 RW D890_000Fh
4h Control 1 register (CTRL1) 32 RW 0000_0000h
8h Free Running Timer (TIMER) 32 RW 0000_0000h
10h Rx Mailboxes Global Mask register (RXMGMASK) 32 RW Table 49-5
Table continues on the next page...
Memory map/register definition
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
1574 NXP Semiconductors