NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 1663 / 1761

3. Write the EMPTY code (0b0100) to the CODE field of the Control and Status word
to activate the mailbox. No setup is required for EDL, BRS, and ESI bits—they are
overwritten by the respective bit fields in the received message.
After the MB is activated, it will be able to receive frames that match the programmed
filter. At the end of a successful reception, the mailbox is updated by the move-in process
(see
Move-in ) as follows:
1. The received data field (8 bytes at most for Classical CAN message format and up to
64 bytes for CAN FD message format) is stored.
2. The received Identifier field is stored.
3. The value of the Free Running Timer at the time of the second bit of frame's
Identifier field is written into the mailbox's Time Stamp field.
4. The received SRR, IDE, RTR, EDL, BRS, ESI, and DLC fields are stored.
5. The CODE field in the Control and Status word is updated (see
Table 49-10 and
Table 49-11 in Section Message buffer structure ).
6. A status flag is set in the Interrupt Flag Register and an interrupt is generated if
allowed by the corresponding Interrupt Mask Register bit.
The recommended way for the CPU to service (read) the frame received in a mailbox is
by the following procedure:
1. Read the Control and Status word of that mailbox.
2. Check if the BUSY bit is deasserted, indicating that the mailbox is locked. Repeat
step 1) while it is asserted. See Mailbox lock mechanism .
3. Read the contents of the mailbox. After the mailbox is locked, its contents won't be
modified by FlexCAN move-in processes. See Move-in .
4. Acknowledge the proper flag at IFLAG registers.
5. Read the free running timer. It is optional but recommended to unlock the mailbox as
soon as possible and make it available for reception.
The CPU should poll for frame reception by the status flag bit for the specific mailbox in
one of the IFLAG registers and not by the CODE field of that mailbox. Polling the
CODE field does not work because after a frame is received and the CPU services the
mailbox (by reading the C/S word followed by unlocking the mailbox), the CODE field
will not return to EMPTY. It will remain FULL, as explained in
Table 49-10 . If the CPU
tries to work around this behavior by writing to the C/S word to force an EMPTY code
after reading the mailbox without a prior safe inactivation, a newly received frame
matching the filter of that mailbox may be lost.
CAUTION
In summary: never do polling by reading directly the C/S word
of the mailboxes. Instead, read the IFLAG registers.
Chapter 49 FlexCAN
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 1663