NXP Semiconductors MWCT101 S Series, Reference Manual

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cleared if the command misses. In general, if the valid indicator (CLCR[LCIVB] is
cleared, the targeted line was invalid at the start of the line command and no line
operation was performed.
Table 29-5. Line command results
CLCR[22:20] For cache address commands For physical address commands
LCWA
Y
LCIMB LCIVB
0 0 0 Way 0 line was invalid No hit
0 0 1 Way 0 valid, not modified Way 0 valid, not modified
0 1 0 Way 0 line was invalid No hit
0 1 1 Way 0 valid and modified Way 0 valid and modified
1 0 0 Way 1 line was invalid No hit
1 0 1 Way 1 valid, not modified Way 1 valid, not modified
1 1 0 Way 1 line was invalid No hit
1 1 1 Way 1 valid and modified Way 1 valid and modified
At completion of a line command other than a write, the CCVR (Cache R/W Value
Register) contains information on the initial state of the line tag or data targeted by the
command. For line commands, CLCR[TDSEL] selects between tag and data. If the line
command used a physical address and missed, the data is don't care. For write commands,
the CCVR holds the write data.
Functional Description
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
656 NXP Semiconductors