NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 1557 / 1761

Table 48-9. SPI Slave (CPHA=0) Configuration (continued)
Register Value Comments
support MSB first transfer by writing to
SHIFTBUFBBS register instead.
SHIFTBUF(n+1) Data to receive Received data can be read from
SHIFTBUFBYS, use the Shifter Status
Flag to indicate when data can be read
using interrupt or DMA request. Can
support MSB first transfer by reading
from SHIFTBUFBIS register instead.
Table 48-10. SPI Slave (CPHA=1) Configuration
Register Value Comments
SHIFTCFGn 0x0000_0001 Shifter configured to load on first shift
and stop bit disabled.
SHIFTCTLn 0x0003_0002 Configure transmit using Timer 0 on
rising edge of shift clock with output data
on Pin 0.
SHIFTCFG(n+1) 0x0000_0000 Start and stop bit disabled.
SHIFTCTL(n+1) 0x0080_0101 Configure receive using Timer 0 on
falling edge of shift clock with input data
on Pin 1.
TIMCMPn 0x0000_003F Configure 32-bit transfer. Set
TIMCMP[15:0] = (number of bits x 2) - 1.
TIMCFGn 0x0120_6602 Configure start bit, enable on trigger
rising edge, disable on trigger falling
edge, initial clock state is logic 0 and
decrement on pin input.
TIMCTLn 0x06C0_0203 Configure 16-bit counter using Pin 2
input (shift clock), with Pin 3 input (slave
select) as the inverted trigger.
SHIFTBUFn Data to transmit Transmit data can be written to
SHIFTBUF, use the Shifter Status Flag
to indicate when data can be written
using interrupt or DMA request. Can
support MSB first transfer by writing to
SHIFTBUFBBS register instead.
SHIFTBUF(n+1) Data to receive Received data can be read from
SHIFTBUFBYS, use the Shifter Status
Flag to indicate when data can be read
using interrupt or DMA request. Can
support MSB first transfer by reading
from SHIFTBUFBIS register instead.
Chapter 48 Flexible I/O (FlexIO)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 1557