NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 1400 / 1761

Table 45-8. LPSPI Command Word in Master Mode (continued)
Transmit Command Register
(TCR)
Description Can this bit/
field be
modified
during a
data
transfer?
Bit/Field Name
PCS Peripheral Chip
Select
Configures which LPSPI_PCS asserts for the transfer; the polarity of
LPSPI_PCS is static and configured by PCSPOL. If PCSCFG is set, then
PCS[3:2] should not be selected. N
LSBF LSB First Configures if LSB (bit 0) or MSB (bit 31 for a 32-bit word) is transmitted
or received first. Y
BYSW Byte Swap Enables byte swap on each 32-bit word when transmitting and receiving
data. Byte swapping can be useful when interfacing to devices that
organize data as big-endian. Y
CONT Continuous Transfer Configures for a continuous transfer that keeps PCS asserted between
frames (as configured by FRAMESZ). A new command word is required
to cause PCS to negate. Also supports changing the command word at
the frame size boundaries.
Y
CONTC Continuing
Command
Indicates that this is a new command word for the existing continuous
transfer. The CONTC bit when set must only be written to the transmit/
command FIFO on a frame bounday. Y
RXMSK Receive Data Mask Masks the receive data and does not store the masked receive data to
the receive FIFO or perform receive data matching. Useful for half-duplex
transfers or to configure which fields are compared during receive data
matching.
Y
TXMSK Transmit Data Mask Masks the transmit data, so that masked transmit data is not pulled from
transmit FIFO, and the output data pin is tristated (unless configured by
Output Config CFGR1[OUTCFG]). Useful for half-duplex transfers.
Y
WIDTH Transfer Width Configures the number of bits shifted on each LPSPI_SCK pulse.
• 1-bit transfers support traditional SPI bus transfers in either half-
duplex or full-duplex data formats.
• 2-bit and 4-bit transfers are useful for interfacing to QuadSPI
memory devices, and only support half-duplex data formats, and at
least one bit (Transmit Data Mask (TCR[TXMSK] or Receive Data
Mask TCR[RXMSK]) must also be set.
Y
FRAMESZ Frame Size Configures the frame size in number of bits equal to (F 1).
• The minimum frame size is 8 bits.
• The minimum word size is 2 bits; a frame size of 33 bits (or similar)
is not supported.
• If the frame size is larger than 32 bits, then the frame is divided into
multiple words of 32-bits; each word is loaded from the transmit
FIFO and stored in the receive FIFO separately.
• If the size of the frame is not divisible by 32, then the last load of
the transmit FIFO and store of the receive FIFO will contain the
remainder bits. For example, a 72-bit transfer will consist of 3
words: the 1st and 2nd words are 32-bit, and the 3rd word is 8-bit.
Y
SPI bus transfers:
• The LPSPI initiates a SPI bus transfer when:
• data is written to the transmit FIFO
Functional description
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
1400 NXP Semiconductors