NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 1414 / 1761

46.2.4 Signal Descriptions
Table 46-3. Signals
Signal Name 2-Wire Scheme 4-Wire Scheme I/O
SCL LPI2C clock
line
SCL In 4-wire mode, this is the SCL input pin. I/O
SDA LPI2C data
line
SDA In 4-wire mode, this is the SDA input pin. I/O
HREQ Host request If host request is asserted and the I2C bus is idle, then it will initiate an LPI2C
master transfer.
I
SCLS Secondary
I2C clock line
Not used In 4-wire mode, this is the SCLS output pin. If
LPI2C master/slave are configured to use
separate pins, then this the LPI2C slave SCL
pin. I/O
SDAS Secondary
I2C data line
Not used In 4-wire mode, this is the SDAS output pin. If
LPI2C master/slave are configured to use
separate pins, then this the LPI2C slave SDA
pin. I/O
46.2.5 Wiring options
LPI2C can be used to implement 2-wire or 4-wire I
2
C serial busses.
Printed Circuit Board (PCB)
I²C (Inter-Integrated Circuit) 2-Wire Serial Bus
Microcontroller
2-wire
peripheral
device #1
2-wire
peripheral
device #2
2-wire
peripheral
device #3
Data (SDA)
Clock (SCL)
MCU
Slave Slave Slave
Figure 46-5. 2-Wire scheme
Some applications can provide a lot of load and noise on the I
2
C bus; to ensure robust I
2
C
operations, a 4-wire interface with the MCU can be used, splitting the 2 lines into inputs
and outputs. Using a few transistors, resistors and diodes, designers can make their own
inexpensive line drivers.
Introduction
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
1414 NXP Semiconductors