NXP Semiconductors MWCT101 S Series, Reference Manual

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channel (n) input
synchronizer
filter
dual edge capture
mode logic
is filter
enabled?
FTM counter
CLK CLK
D Q D Q
0
1
FTM input clock
CLK
D Q
FTM filter clock
channel (n)
interrupt
CnV
CHIE
CHF
channel (n)
channel (n+1)
interrupt
CnV
CHIE
CHF
channel (n+1)
Figure 41-95. Diagram for Dual Edge Capture Mode when FLTPS[3:0] ≠ 0
The channel (n) MSA bit defines if the dual edge capture mode is one-shot or continuous.
The channel (n) ELSB:ELSA bits select the edge that is captured by channel (n), and
channel (n+1) ELSB:ELSA bits select the edge that is captured by channel (n+1). If both
channel (n) ELSB:ELSA and channel (n+1) ELSB:ELSA bits select the same edge, then
it is the period measurement. If these bits select different edges, then it is a pulse width
measurement.
In the dual edge capture mode, only channel (n) input is used and channel (n+1) input is
ignored.
If the selected edge by channel (n) bits is detected at channel (n) input, then channel (n)
CHF bit is set and the channel (n) interrupt is generated (if channel (n) CHIE = 1). If the
selected edge by channel (n+1) bits is detected at channel (n) input and (channel (n) CHF
= 1), then channel (n+1) CHF bit is set and the channel (n+1) interrupt is generated (if
channel (n+1) CHIE = 1).
The C(n)V register stores the FTM counter value when the selected edge by channel (n)
is detected at channel (n) input. The C(n+1)V register stores the FTM counter value when
the selected edge by channel (n+1) is detected at channel (n) input.
In this mode, a coherency mechanism (for channels (n) and (n+1)) ensures coherent data
when the C(n)V and C(n+1)V registers are read. The only requirement is that C(n)V must
be read before C(n+1)V.
Note
• The dual edge capture mode must be used with channel (n)
ELSB:ELSA = 0:1 or 1:0, channel (n+1) ELSB:ELSA =
0:1 or 1:0 and the FTM counter in
Free running counter .
Functional Description
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
1258 NXP Semiconductors