NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 106 / 1761

8.3 Memory map/register descriptions
The memory map and register descriptions below describe the Miscellaneous Control
Module registers.
NOTE
• All registers are accessible only in Supervisor mode. User
mode accesses will generate an error.
• Writing to read-only MCM_PLASC and MCM_PLAMC
registers, would generate a bus error.
MCM memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
E008_0008
Crossbar Switch (AXBS) Slave Configuration
(MCM_PLASC)
16 R 0007h 8.3.1/107
E008_000A
Crossbar Switch (AXBS) Master Configuration
(MCM_PLAMC)
16 R 0007h 8.3.2/107
E008_000C Core Platform Control Register (MCM_CPCR) 32 R/W See section 8.3.3/109
E008_0010 Interrupt Status and Control Register (MCM_ISCR) 32 R 0002_0000h 8.3.4/112
E008_0030 Process ID Register (MCM_PID) 32 R/W 0000_0000h 8.3.5/115
E008_0040 Compute Operation Control Register (MCM_CPO) 32 R/W 0000_0000h 8.3.6/116
E008_0400 Local Memory Descriptor Register (MCM_LMDR0) 32 R/W See section 8.3.7/117
E008_0404 Local Memory Descriptor Register (MCM_LMDR1) 32 R/W See section 8.3.7/117
E008_0408 Local Memory Descriptor Register2 (MCM_LMDR2) 32 R/W 8424_40A0h 8.3.8/120
E008_0480 LMEM Parity and ECC Control Register (MCM_LMPECR) 32 R/W 0000_0000h 8.3.9/124
E008_0488 LMEM Parity and ECC Interrupt Register (MCM_LMPEIR) 32 R/W 0000_0000h 8.3.10/124
E008_0490 LMEM Fault Address Register (MCM_LMFAR) 32 R 0000_0000h 8.3.11/126
E008_0494 LMEM Fault Attribute Register (MCM_LMFATR) 32 R 0000_0000h 8.3.12/127
E008_04A0 LMEM Fault Data High Register (MCM_LMFDHR) 32 R 0000_0000h 8.3.13/128
E008_04A4 LMEM Fault Data Low Register (MCM_LMFDLR) 32 R 0000_0000h 8.3.14/128
Memory map/register descriptions
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
106 NXP Semiconductors