NXP Semiconductors MWCT101 S Series, Reference Manual

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46.4.3.2 Transmit and Receive Data
• The Transmit and Receive Data registers are double-buffered and only update during
a slave-transmit and slave-receive transfer, respectively.
• The slave address that was received can be configured to be read from either the
Receive Data register (for example, when using DMA to transfer data), or from the
Address Status register.
• The Transmit Data register can be configured to only request data after a slave-
transmit transfer is detected, or to request new data whenever the Transmit Data
register is empty.
• The Transmit Data register should only be written when the Transmit Data flag is set.
• The Receive Data register should only be read when the Received Data flag is set (or
the Address Valid flag is set and RXCFG=1).
• The Address Status register should only be read when the Address Valid flag is set.
46.4.3.3 Clock Stretching
The LPI2C slave supports many configurable options for when clock stretching is
performed. The following conditions can be configured to perform clock stretching:
• During the 9th clock pulse of the address byte and the Address Valid flag is set.
• During the 9th clock pulse of a slave-transmit transfer and the Transmit Data flag is
set.
• During the 9th clock pulse of a slave-receive transfer and the Receive Data flag is
set.
• During the 8th clock pulse of an address byte or a slave-receive transfer and the
Transmit ACK flag is set. In high speed mode, this is disabled.
• Clock stretching can also be extended for CLKHOLD cycles, to allow additional
setup time to sample the SDA pin externally. In high speed mode, this is disabled.
Unless extended by the CLKHOLD configuration, clock stretching will extend for one
peripheral bus clock cycle after SDA updates when clock stretching is enabled.
46.4.3.4 Timing Parameters
The LPI2C slave can configure the following timing parameters. These parameters are
disabled when SCR[FILTEN] is clear, when SCR[FILTDZ] is set in Doze mode, and
when LPI2C slave detects high speed mode. When disabled, the LPI2C slave is clocked
directly from the I2C bus, and may not satisfy all timing requirements of the I2C
specification (such as SDA minimum hold time in Standard/Fast mode).
Functional description
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
1462 NXP Semiconductors