The bytes not assigned to data flash via the FlexNVM partition code are used by the
FTFC to obtain an effective endurance increase for the EEPROM data. The built-in
emulated EEPROM record management system raises the number of program/erase
cycles that can be attained prior to device wear-out by cycling the EEPROM data through
a larger emulated EEPROM NVM storage space.
While different partitions of the FlexNVM are available, the intention is that a single
choice for the FlexNVM partition code and emulated EEPROM data set size is used
throughout the entire lifetime of a given application.
Normal EEE writes and quick writes should not be used in an aggressive brownout
environment (e.g., multiple back-to-back brownouts without recovery in between).
32.5.2.5 ECC implementation for FlexNVM
When the FlexNVM region is configured as Data Flash, any single-bit ECC errors are
automatically corrected, and any double-bit ECC errors are reflected onto
FERSTAT[DFDIF] flag at the read access from Data Flash.
When the FlexNVM region is configured as Emulated EEPROM, any single-bit ECC
errors are automatically corrected before copying data into EEERAM at the read access
from Emulated EEPROM, and any double-bit ECC errors on valid Emulated EEPROM
locations which containing data that need to be copied to EEERAM are reflected as the
corresponding data records left as all 1's in EEERAM.
32.5.3 Interrupts
The FTFC module can generate interrupt requests to the MCU upon the occurrence of
various FTFC events. These interrupt events and their associated status and control bits
are shown in the following table.
Table 32-16. FTFC interrupt sources
FTFC Event
Readable
Status Bit
Interrupt
Enable Bit
FTFC Command and CSEc command Complete
FSTAT[CCIF]
FCNFG[CCIE]
FTFC Read Collision Error
FSTAT[RDCOLERR]
FCNFG[RDCOLLIE]
FTFC ECC Error Detection
FERSTAT[DFDIF]
FERCNFG[DFDIE]
Chapter 32 Flash Memory Module (FTFC)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors
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Summary of Contents for MWCT101 S Series
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Page 50: ...Conventions MWCT101xS Series Reference Manual Rev 3 07 2019 50 NXP Semiconductors...
Page 70: ...Aliased bit band regions MWCT101xS Series Reference Manual Rev 3 07 2019 70 NXP Semiconductors...
Page 78: ...Pinout diagrams MWCT101xS Series Reference Manual Rev 3 07 2019 78 NXP Semiconductors...
Page 96: ...WCT101xS safety concept MWCT101xS Series Reference Manual Rev 3 07 2019 96 NXP Semiconductors...
Page 130: ...Functional description MWCT101xS Series Reference Manual Rev 3 07 2019 130 NXP Semiconductors...
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Page 472: ...Application Information MWCT101xS Series Reference Manual Rev 3 07 2019 472 NXP Semiconductors...
Page 528: ...Module clocks MWCT101xS Series Reference Manual Rev 3 07 2019 528 NXP Semiconductors...
Page 634: ...SRAM configuration MWCT101xS Series Reference Manual Rev 3 07 2019 634 NXP Semiconductors...
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Page 992: ...ADC calibration scheme MWCT101xS Series Reference Manual Rev 3 07 2019 992 NXP Semiconductors...
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Page 1726: ...Debug and security MWCT101xS Series Reference Manual Rev 3 07 2019 1726 NXP Semiconductors...
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