NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 238 / 1761

Table 14-1. Register reset values (continued)
Register WCT1014S WCT1015S WCT1016S
OPACRA 4400_4444 4400_4444 4400_4444
OPACRB 0000_4400 0000_4400 0004_4440
OPACRC 0440_0044 0440_0044 0440_0044
OPACRD 4444_0400 4444_0400 4444_0400
OPACRE 4000_0040 4000_0040 4000_0040
OPACRF 4444_4400 4444_4400 4444_4400
OPACRG 0040_0000 0040_0000 0040_4400
OPACRH 0040_0000 0040_0000 0040_0000
OPACRI 0404_4440 0404_4440 0404_4444
OPACRJ 0044_0000 0044_4044 0044_4044
OPACRK 0004_0000 0004_0000 4404_0040
OPACRL 0000_0444 0000_0444 0400_0444
14.2 Introduction
The peripheral bridge converts the crossbar switch interface to an interface that can
access most of the slave peripherals on this chip.
The peripheral bridge occupies 64 MB of the address space, which is divided into
peripheral slots of 4 KB. (It might be possible that all the peripheral slots are not used.
See the memory map chapter for details on slot assignments.) The bridge includes
separate clock enable inputs for each of the slots to accommodate slower peripherals.
14.2.1 Features
Key features of the peripheral bridge are:
• Supports peripheral slots with 8-, 16-, and 32-bit datapath width
• Programming model provides memory protection functionality
14.2.2 General operation
The slave devices connected to the peripheral bridge are modules which contain a
programming model of control and status registers. The system masters read and write
these registers through the peripheral bridge.
Introduction
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
238 NXP Semiconductors