NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 1611 / 1761

49.4.2.16.4 Fields
Field Function
31-9
—
Reserved
8-0
IDHIT
Identifier Acceptance Filter Hit Indicator
This field indicates which Identifier Acceptance filter was hit by the received message that is in the output
of the Rx FIFO. If multiple filters match the incoming message ID then the first matching IDAF found
(lowest number) by the matching process is indicated. This field is valid only when IFLAG1[BUF5I] is
asserted.
49.4.2.17 CAN Bit Timing register (CBT)
49.4.2.17.1 Offset
Register Offset
CBT 50h
49.4.2.17.2 Function
This register is an alternative way to store the CAN bit timing variables described in
CTRL1 register. EPRESDIV, EPROPSEG, EPSEG1, EPSEG2, and ERJW are extended
versions of PRESDIV, PROPSEG, PSEG1, PSEG2, and RJW fields respectively.
The BTF bit selects the use of the timing variables defined in this register.
The contents of this register are not affected by soft reset.
NOTE
The CAN bit variables in CTRL1 and in CBT are stored in the
same register.
NOTE
When the CAN FD feature is enabled (MCR[FDEN] is set),
always set CBT[BTF].
NOTE
The user must ensure bit time settings and protocol engine
tolerance are in compliance with the CAN Protocol standard
(ISO 11898-1).
Chapter 49 FlexCAN
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 1611