NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 1485 / 1761

Field Function
TIE Enables STAT[TDRE] to generate interrupt requests.
0b - Hardware interrupts from TDRE disabled; use polling.
1b - Hardware interrupt requested when TDRE flag is 1.
22
TCIE
Transmission Complete Interrupt Enable for
TCIE enables the transmission complete flag, TC, to generate interrupt requests.
0b - Hardware interrupts from TC disabled; use polling.
1b - Hardware interrupt requested when TC flag is 1.
21
RIE
Receiver Interrupt Enable
Enables STAT[RDRF] to generate interrupt requests.
0b - Hardware interrupts from RDRF disabled; use polling.
1b - Hardware interrupt requested when RDRF flag is 1.
20
ILIE
Idle Line Interrupt Enable
ILIE enables the idle line flag, STAT[IDLE], to generate interrupt requests.
0b - Hardware interrupts from IDLE disabled; use polling.
1b - Hardware interrupt requested when IDLE flag is 1.
19
TE
Transmitter Enable
Enables the LPUART transmitter. TE can also be used to queue an idle preamble by clearing and then
setting TE. When TE is cleared, this register bit will read as 1 until the transmitter has completed the
current character and the TXD pin is tristated.
A single idle character can also be queued by writing to the transmit FIFO with DATA[FRETSC] set and
DATA[R9T9] set.
0b - Transmitter disabled.
1b - Transmitter enabled.
18
RE
Receiver Enable
Enables the LPUART receiver. When RE is written to 0, this register bit will read as 1 until the receiver
finishes receiving the current character (if any).
0b - Receiver disabled.
1b - Receiver enabled.
17
RWU
Receiver Wakeup Control
This field can be set to place the LPUART receiver in a standby state. RWU automatically clears when an
RWU event occurs, that is, an IDLE event when CTRL[WAKE] is clear or an address match when
CTRL[WAKE] is set with STAT[RWUID] is clear.
NOTE: RWU must be set only with CTRL[WAKE] = 0 (wakeup on idle) if the channel is currently not
idle. This can be determined by STAT[RAF]. If the flag is set to wake up an IDLE event and the
channel is already idle, it is possible that the LPUART will discard data. This is because the data
must be received or a LIN break detected after an IDLE is detected before IDLE is allowed to be
reasserted.
0b - Normal receiver operation.
1b - LPUART receiver in standby waiting for wakeup condition.
16
SBK
Send Break
Writing a 1 and then a 0 to SBK queues a break character in the transmit data stream. Additional break
characters of 9 to 13 bits, or 12 to 15 bits if STAT[BRK13] is set, bit times of logic 0 are queued as long
as SBK is set. Depending on the timing of the set and clear of SBK relative to the character currently
being transmitted, a second break character may be queued before software clears SBK.
A single break character can also be queued by writing to the transmit FIFO with DATA[FRETSC] set and
DATA[R9T9] clear.
0b - Normal transmitter operation.
1b - Queue break character(s) to be sent.
Table continues on the next page...
Chapter 47 Low Power Universal Asynchronous Receiver/Transmitter (LPUART)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 1485