NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 317 / 1761

16.4.5.9 Set Enable Request Register (SERQ)
16.4.5.9.1 Offset
Register Offset
SERQ 1Bh
16.4.5.9.2 Function
The SERQ provides a simple memory-mapped mechanism to set a given bit in the ERQ
to enable the DMA request for a given channel. The data value on a register write causes
the corresponding bit in the ERQ to be set. Setting the SAER bit provides a global set
function, forcing the entire contents of ERQ to be set.
If the NOP bit is set, the command is ignored. This allows you to set a single, byte-wide
register with a 32-bit write while not affecting the other registers addressed in the write.
In such a case the other three bytes of the word would all have their NOP bit set so that
that these register will not be affected by the write.
Reads of this register return all zeroes.
16.4.5.9.3 Diagram
Bits
7 6 5 4 3 2 1 0
R
0 0 0
W
NOP
SAE R
0
SER Q
Reset
0 0 0 0 0 0 0 0
16.4.5.9.4 Fields
Field Function
7
NOP
No Op enable
0b - Normal operation
1b - No operation, ignore the other bits in this register
6
SAER
Set All Enable Requests
0b - Set only the ERQ bit specified in the SERQ field
1b - Set all bits in ERQ
5-4
—
Reserved
Table continues on the next page...
Chapter 16 Enhanced Direct Memory Access (eDMA)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 317