NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 1315 / 1761

42.4.1.11.2 Function
The Timer Control registers contain the control bits for each timer channel.
NOTE
• Unless the peripheral clock to the timers is enabled
(Module Clock Enable bit (MCR[M_CEN]) is set (=1)),
then reading or writing the Timer Control register will
generate a transfer error.
• Timer controls should only be updated when the timer is
disabled. In the Timer Control Register TCTRLn, these
timer controls include:
• Trigger Select TRG_SEL
• Trigger Source TRG_SRC
• Timer Reload On Trigger TROT
• Timer Stop On Interrupt TSOI
• Timer Start On Trigger TSOT
• Timer Operation Mode MODE
• Chain Channel CHAIN
There are 2 ways to disable a timer: write 1 to the specific
timer's Clear Timer Enable register bit
(CLRTEN[CLR_T_EN_n]) or set the timer enable bit
(TCTRLn[T_EN]) = 0 for that channel.
42.4.1.11.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
TRG_SE L
TRG_SR C
0
TROT
TSOI
TSOT
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
MODE
CHAIN
T_E N
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
42.4.1.11.4 Fields
Field Function
31-28 This read-only field is reserved and always has the value 0
Table continues on the next page...
Chapter 42 Low Power Interrupt Timer (LPIT)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 1315