NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 222 / 1761

13.4.10.4 Fields
Field Function
31
M7RE
Bus Master 7 Read Enable
0b - Bus master 7 reads terminate with an access error and the read is not performed
1b - Bus master 7 reads allowed
30
M7WE
Bus Master 7 Write Enable
0b - Bus master 7 writes terminate with an access error and the write is not performed
1b - Bus master 7 writes allowed
29
M6RE
Bus Master 6 Read Enable
0b - Bus master 6 reads terminate with an access error and the read is not performed
1b - Bus master 6 reads allowed
28
M6WE
Bus Master 6 Write Enable
0b - Bus master 6 writes terminate with an access error and the write is not performed
1b - Bus master 6 writes allowed
27
M5RE
Bus Master 5 Read Enable
0b - Bus master 5 reads terminate with an access error and the read is not performed
1b - Bus master 5 reads allowed
26
M5WE
Bus Master 5 Write Enable
0b - Bus master 5 writes terminate with an access error and the write is not performed
1b - Bus master 5 writes allowed
25
M4RE
Bus Master 4 Read Enable
0b - Bus master 4 reads terminate with an access error and the read is not performed
1b - Bus master 4 reads allowed
24
M4WE
Bus Master 4 Write Enable
0b - Bus master 4 writes terminate with an access error and the write is not performed
1b - Bus master 4 writes allowed
23
—
Reserved
This bit must be written with a zero.
22-21
M3SM
Bus Master 3 Supervisor Mode Access Control
Defines the access controls for bus master 3 in Supervisor mode.
00b - r/w/x; read, write and execute allowed
01b - r/x; read and execute allowed, but no write
10b - r/w; read and write allowed, but no execute
11b - Same as User mode defined in M3UM
20-18
M3UM
Bus Master 3 User Mode Access Control
Defines the access controls for bus master 3 in User mode. M3UM consists of three independent bits,
enabling read (r), write (w), and execute (x) permissions. In M3UM[2:0]: M3UM[2] controls read
permissions, M3UM[1] controls write permissions, and M3UM[0] controls execute permissions. For each
bit:
0b - An attempted access of that mode may be terminated with an access error (if not allowed by
another descriptor) and the access not performed
1b - Allows the given access type to occur
17
—
Reserved
This bit must be written with a zero.
16-15
M2SM
Bus Master 2 Supervisor Mode Access Control
Defines the access controls for bus master 2 in Supervisor mode.
00b - r/w/x; read, write and execute allowed
01b - r/x; read and execute allowed, but no write
Table continues on the next page...
MPU register descriptions
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
222 NXP Semiconductors