NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 694 / 1761

31.5.1 Default configuration
Upon system reset, the FMC is configured to provide a significant level of buffering for
transfers from the flash memory or FlexMemory:
• For bank 0 and bank 1:
• Prefetch support for data and instructions is enabled.
• The single-entry buffer is enabled.
31.5.2 Speculative reads
The FMC has a single buffer that reads ahead to the next word in the flash memory if
there is an idle cycle. Speculative prefetching is programmable for each bank for
instruction and/or data accesses using MSCM_OCMDR0[5] and MSCM_OCMDR1[5]
(value 0 means "enables prefetches (or speculative accesses)"). Because many code
accesses are sequential, using the speculative prefetch buffer improves performance in
most cases.
When speculative reads are enabled, the FMC immediately requests the next sequential
address after a read completes. By requesting the next word immediately, speculative
reads can help to reduce or even eliminate wait states when accessing sequential code
and/or data.
For example, consider the following scenario:
• Assume a system with a 4:1 core-to-flash clock ratio and with speculative reads
enabled.
• The core requests four (for Data Flash, bank 1) or eight (for Program Flash, bank 0)
sequential longwords in back-to-back requests, meaning there are no core cycle
delays except for stalls waiting for flash memory data to be returned.
• None of the data is already stored in the cache or speculation buffer.
In this scenario, the sequence of events for accessing the four (for Data Flash, bank 1)
oreight (for Program Flash, bank 0) longwords is as follows:
1. The first longword read requires 4 to 7 core clocks.
2. Due to the 128-bit data bus of the flash memory, the second longword read takes
only 1 core clock because the data is already available inside the FMC. For the same
reason, the third and fourth longword reads each take only 1 core clock.
3. Per 64-bit for Data Flash (bank 1), accessing the third longword requires 3 core clock
cycles. The flash memory read itself takes 4 clocks, but the first clock overlaps with
the second longword read.
Functional description
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
694 NXP Semiconductors