NXP Semiconductors MWCT101 S Series, Reference Manual

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Field Function
Flash Speculate
(OCMDRn bit 5)
Data Prefetch
(OCMDRn bit 4)
Result
Disabled Disabled All speculation disabled and speculation
buffer is cleared
Disabled Enabled
Enabled Disabled Speculation for Instruction enabled and
Speculation for Data disabled
Enabled Enabled Speculation for both Instruction and Data
enabled
3-0
—
Reserved
30.4.2.19 On-Chip Memory Descriptor Register (OCMDR1)
30.4.2.19.1 Offset
Register Offset
OCMDR1 404h
30.4.2.19.2 Function
This section of the programming model is an array of 32-bit generic on-chip memory
descriptor registers that provide static information about the attached memories, as well
as configurable controls (where appropriate).
• Privileged 32-bit reads from a processor core or the debugger return the appropriate
processor information.
• Reads from any other bus master return all zeroes.
• Privileged writes from a processor core or the debugger to writeable registers update
the appropriate fields.
• Privileged writes from other bus masters are ignored.
• Attempted user mode accesses or any access with a size other than 32 bits are
terminated with an error.
The following table describes the OCMDRn reset values and the associated memory
type:
MSCM Memory Map/Register Definition
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
684 NXP Semiconductors